Real-time bandwidth allocation and path restorations in SONET-based self-healing mesh networks

Gersht, A.; Kheradpir, S.

doi:10.1109/icc.1993.397266

“…Due to its predictable timing behaviour, the real-time system is used at every corner of all industries: an anti-brake system, ATM [6] and SONET network nodes [ 7], MPEG-4/7/21 encoders [8], an airplane controller and a cellular node [ 9]. They are normally classified as one of the following categories: control, adaptive and reactive systems.…”

Section: Real-time Applicationsmentioning

confidence: 99%

“…The methodology identifies the multi-task and multi-mode workload and divides the workload hierarchically according to the dynamic characteristics of the environment. The dynamic characteristics of the environment are modeled as the configuration events 7 . Then the methodology brings the identification to structural and physical representations of the reconfigurable system which associates the physical layout of the programmable device with the multitask and multi-mode workload.…”

Section: Contributionsmentioning

confidence: 99%

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Chun¹

2021

Preprint

0

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Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach

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“…Due to its predictable timing behaviour, the real-time system is used at every corner of all industries: an anti-brake system, ATM [6] and SONET network nodes [ 7], MPEG-4/7/21 encoders [8], an airplane controller and a cellular node [ 9]. They are normally classified as one of the following categories: control, adaptive and reactive systems.…”

Section: Real-time Applicationsmentioning

confidence: 99%

“…The methodology identifies the multi-task and multi-mode workload and divides the workload hierarchically according to the dynamic characteristics of the environment. The dynamic characteristics of the environment are modeled as the configuration events 7 . Then the methodology brings the identification to structural and physical representations of the reconfigurable system which associates the physical layout of the programmable device with the multitask and multi-mode workload.…”

Section: Contributionsmentioning

confidence: 99%

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Chun¹

2021

Preprint

0

View full text Add to dashboard Cite

Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach

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Network Reliability and Fault Tolerance

Médard

¹

,

Lumetta

²

2003

Wiley Encyclopedia of Telecommunications

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This article introduces fundamental concepts in fault tolerance and reliability as applied to networks, with a focus on high‐speed backbone networks. We first introduce basic terminology and elements necessary to fault tolerance, then describe the basic strategies for detecting and handling failures in networks. The discussion then builds on these basics to illustrate recovery schemes for high‐speed backbone networks. An examination of the relationship between network topologies and recovery strategies follows, beginning with rings and then covering more general mesh networks. We cover some basic techniques used in packet‐switched networks, and conclude with a discussion of local‐area network approaches to fault tolerance.

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Real-time bandwidth allocation and path restorations in SONET-based self-healing mesh networks

Cited by 13 publications

References 6 publications

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Network Reliability and Fault Tolerance

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