Real-time H.264/AVC baseline decoder implementation on TMS320C6416

Imen, Werda; Dammak, Taheni; Grandpierre, Thierry; Ayed, Mohamed Ali Ben; Nouri, Mohammad

doi:10.1007/s11554-010-0181-6

Cited by 14 publications

(10 citation statements)

References 14 publications

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“…As it has been shown in different implementation profiles, like the one in [4], DF represents a critical task in H.264/AVC video encoders and decoders The importance of this coding tool increases in the SVC standard, since it can be used not only at the end of the reconstruction loop, but also as part of the inter-prediction step for recovering 978-1-61284-350-6/11/$26.00 ©2011 IEEE information of the enhancement layers from the data contained at the base layer. Furthermore, the computational requirements are highly dependent on the type and levels of scalability which may be dynamically selected by the users.…”

Section: Fig 1 Svc Decoder Diagram Blocksmentioning

confidence: 88%

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs

Cervero

Otero

López

et al. 2011

2011 IEEE International Conference on Multimedia and Expo

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A highly parallel and scalable Deblocking Filter (DF) hardware architecture for H.264/AVC and SVC video codecs is presented in this paper. The proposed architecture mainly consists on a coarse grain systolic array obtained by replicating a unique and homogeneous Functional Unit (FU), in which a whole Deblocking-Filter unit is implemented. The proposal is also based on a novel macroblock-level parallelization strategy of the filtering algorithm which improves the final performance by exploiting specific data dependences.This way communication overhead is reduced and a more intensive parallelism in comparison with the existing state-of-the-art solutions is obtained. Furthermore, the architecture is completely flexible, since the level of parallelism can be changed, according to the application requirements. The design has been implemented in a Virtex-5 FPGA, and it allows filtering 4CIF (704x576 pixels @30fps) video sequences in real-time at frequencies lower than 10.16 Mhz.Index Terms-H.264/AVC, SVC, deblocking-filter, FPGA, parallelism and scalability.

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Section: Fig 1 Svc Decoder Diagram Blocksmentioning

confidence: 88%

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs

Cervero

Otero

López

et al. 2011

2011 IEEE International Conference on Multimedia and Expo

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“…Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TCSVT.2019.2954474 [115][116][117][118][119] and HEVC decoder [120][121][122][123], research on HEVC encoders implementation is relatively rare. The high complexity of HEVC encoders, which is tens of times larger than that of HEVC decodes as well as H.264/AVC, making it very demanding however challenging.…”

Section: Dsp-based Implementationmentioning

confidence: 99%

Recent Advances on HEVC Inter-Frame Coding: From Optimization to Implementation and Beyond

Zhang

Fan

et al. 2020

IEEE Trans. Circuits Syst. Video Technol.

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High Efficiency Video Coding (HEVC) has doubled the video compression ratio with equivalent subjective quality as compared to its predecessor H.264/AVC. The significant coding efficiency improvement is attributed to many new techniques. Interframe coding is one of the most powerful yet complicated techniques therein and has posed high computational burden thus main obstacle in HEVC-based real-time applications. Recently, plenty of research has been done to optimize the inter-frame coding, either to reduce the complexity for real-time applications, or to further enhance the encoding efficiency. In this paper, we provide a comprehensive review of the state-of-the-art techniques for HEVC inter-frame coding from three aspects, namely fast inter coding solutions, implementation on different hardware platforms as well as advanced inter coding techniques. More specifically, different algorithms in each aspect are further subdivided into sub-categories and compared in terms of pros, cons, coding efficiency and coding complexity. To the best of our knowledge, this is the first such comprehensive review of the recent advances of the inter-frame coding for HEVC and hopefully it would help the improvement, implementation and applications of HEVC as well as the ongoing development of the next generation video coding standard.

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“…Our choice for using this multicore DSP platform enables us to develop an academic H264/AVC codec [34] in our LETI laboratory (Laboratory of Electronics and Information Technologies) for future research and development targeting embedded video applications. Standard compliant LETI's codec was developed and tested first on a PC environment for validation and then migrated to TMS320C6472 DSP platform.…”

Section: Optimized Implementation On a Single Dsp Corementioning

confidence: 99%

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

Bahri

Belhadj²,

Grandpierre³

et al. 2014

J Real-Time Image Proc

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International audienceThe latest generation of multicore digital signal processors (DSP), their high computing power, low consumption, and integrated peripherals will allow them to be embedded in the next generation of smart camera. Such DSPs allow designers to evolve the vision landscape and simplify the developer’s tasks to run more complex image and video processing applications without the need to burden a separate personal computer. This paper explains the exploitation of the computing power of a multicore DSP TMS320C6472 to implement a real-time H264/AVC video encoder. This work can be considered as a milestone for the implementation of the new High Efficiency Video Coding standard (HEVC-H265). In fact, to improve the encoding speed, enhanced Frame Level Parallelism (FLP) approach is presented and implemented. A real-time fully functional video demo is given, taken into account video capture and bitstream storage. Experimental results show how we efficiently exploit the potentials and the features of the multicore platform without inducing video quality degradation in terms of PSNR or bitrate increase. The enhanced FLP using five DSP cores achieves a speedup factor of more than four times in average compared to a mono-core implementation for Common Intermediate Format (CIF 352 × 288), Standard Definition (SD 720 × 480), and High Definition (HD 1280 × 720) resolutions. This optimized implementation allows us to meet the real-time compliant by reaching an encoding speed of 99 f/s (frame/second) and 30 f/s for CIF and SD resolutions respectively, and saves up to 77 % of encoding time for HD resolution

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Real-time H.264/AVC baseline decoder implementation on TMS320C6416

Cited by 14 publications

References 14 publications

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs

Recent Advances on HEVC Inter-Frame Coding: From Optimization to Implementation and Beyond

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

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