Real-time high-definition stereo matching on FPGA

Zhang, Lu; Zhang, Ke; Chang, Tian-Sheuan; Lafruit, Gauthier; Kuzmanov, Georgi; Verkest, D.

doi:10.1145/1950413.1950428

Cited by 73 publications

(51 citation statements)

References 12 publications

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“…A 52% improvement in FPS is observed when the proposed methodology is compared with one of the recently reported design [9]. In particular LUT utilization is reduced by 61.5%, 40.5%, 43.2%, 72.7%, 35.6% when compared to latest reported results in [9], [13], [22], [25], [35] respectively. Slice registers utilization is reduced by 59.6%, 33.46%, 41.6%, 36% when compared to [9], [13], [22], [25] respectively.…”

Section: Resultsmentioning

confidence: 64%

See 1 more Smart Citation

High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

Vala

Immadisetty

Acharyya

et al. 2018

IEEE Trans. Circuits Syst. I

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Abstract-Stereo vision is a methodology to obtain depth in a scene based on the stereo image pair. In this paper we introduce a Discrete Wavelet Transform (DWT) based methodology for a state-of-the-art disparity estimation algorithm, that resulted in significant performance improvement in terms of speed and computational complexity. In the initial stage of the proposed algorithm, we apply DWT to the input images, reducing the number of samples to be processed in subsequent stages by 50%, thereby decreasing computational complexity and improving processing speed. Subsequently the architecture has been designed based on this proposed methodology and prototyped on a Xilinx Virtex-7 FPGA. The performance of the proposed methodology has been evaluated against four standard Middlebury Benchmark image pairs viz. Tsukuba, Venus, Teddy and Cones. The proposed methodology results in improvement of about 44.4% cycles per frame, 52% frames per second and 61.5% and 59.6% LUT and register utilization respectively, compared with state-of-the-art designs.

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Section: Resultsmentioning

confidence: 64%

“…al. combined both the mini-census transform and cross based cost aggregation for implementing real-time FPGA based stereo matching [25]. SGM-based stereo matching systems have been introduced in [8], [9], [15] and implemented on FPGAs and a hybrid FPGA/RISC architecture based platforms respectively.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

Vala

Immadisetty

Acharyya

et al. 2018

IEEE Trans. Circuits Syst. I

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show abstract

“…The hardware resources required are fairly low compared to other approaches. Zhang et al (2011) requires about 95000 logic blocks and 3.77 MBit of memory at the Stratix III, compared to ca 40000 logic blocks and 321 kBit of memory needed for the presented solution with a disparity range of 64 px (disparity range of 256 px used for this research (⇒ ca 147000 logic blocks and 328 kBit). The approach presented by Jin et al (2010), implemented on a Virtex 4, needs 51000 logic elements and 322 memory blocks compared to the Virtex 6 implementation with a disparity range of 64 px with 39000 logic elements and 23 memory blocks (disparity range of 256 px ⇒ ca 149000 logic blocks 23 memory blocks).…”

Section: Comparison With the State Of The Art Of Stereo Image Analysimentioning

confidence: 99%

“…The rate of incorrect points in the depth map ranges from 14 % in Zhang et al (2011) to 17 % in Jin et al (2010). The hardware resources required are fairly low compared to other approaches.…”

Section: Comparison With the State Of The Art Of Stereo Image Analysimentioning

confidence: 99%

Fast Computation of Dense and Reliable Depth Maps from Stereo Images

Tornow¹,

Grasshoff²,

Nguyen³

et al. 2012

Machine Vision - Applications and Systems

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“…Abdulkadir et al [5] proposed a new algorithm named AWDE, which is very suitable to be implement on hardware, they implemented their algorithm on Xilinx Vitex-5 and can achieve 60 f/ps at resolution of 1024*768 with 128 disparity levels. Zhang et al [6] combine the mini-census transform and cross-based cost aggregation in their structure, which achieves 60 frames/s at 1024×768 pixel stereo images.…”

Section: Stereo Matching Algorithm and Hardware Implementationmentioning

confidence: 99%