Real-Time High-Quality Stereo Vision System in FPGA

Wang, Wenqiang; Yan, Jing; Xu, Ning; Wang, Weichao; Hsu, Feng-Hsiung

doi:10.1109/tcsvt.2015.2397196

Cited by 105 publications

(45 citation statements)

References 20 publications

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“…Table 1 shows the error rates on the Middlebury [20,21] dataset, for a threshold of 1 pixel. The average error rates for [13] and [19] are on a higher side (around 14%) as compared to that of [8,23] and proposed work (8.425, 6 and 8.12%, resp.). A slight increase in error of the proposed implementation as compared to [23] is justified, as SGM with crossbased aggregation is slightly more accurate than with SAD.…”

Section: Accuracymentioning

confidence: 85%

“…The average error rates for [13] and [19] are on a higher side (around 14%) as compared to that of [8,23] and proposed work (8.425, 6 and 8.12%, resp.). A slight increase in error of the proposed implementation as compared to [23] is justified, as SGM with crossbased aggregation is slightly more accurate than with SAD. However, SAD costs can be generated at higher speeds in comparison to cross-based aggregated costs.…”

Section: Accuracymentioning

confidence: 85%

“…For 752 × 480 pixels image, a rate of 60 FPS was achieved at a disparity range of only 32 pixels. A recent SGM implementation with cross-based cost aggregation [23] claims to achieve the highest frame rates for high definition images. The proposed architecture is able to achieve better frame rates than [23].…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching

Jain

Fell

Anand

2017

Procedings of the British Machine Vision Conference 2017

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Semi-Global Matching (SGM) is a popular algorithm to calculate depth maps in stereo images offering the best trade-off among accuracy, computational costs and high frame rates. This paper presents two architectural improvements in FPGA implementations of SGM to achieve high frame rates. First, a highly parallel, pipelined and scalable architecture is implemented which stores the intermediate values internally in the Block-RAMs of the FPGA, rendering external, off-chip memory obsolete. The architecture facilitates the parallelization of the cost computations, over the complete disparity range, in every clock cycle. Secondly, a novel SGM architecture based on multi-clock systems is introduced, which allows the integration of both, disparity-level and row-level parallelism and thus obtain even higher FPS rates. Results show that the FPS obtained are higher than any other FPGA based SGM implementation available in literature. On a Virtex-7 FPGA device, for VGA images (640 × 480 pixels) and a disparity range of 128, a rate of 475 FPS is achieved. A rate as high as 70 FPS is realized for Full-HD images (1920 × 1080 pixels).

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Section: Accuracymentioning

confidence: 85%

Section: Accuracymentioning

confidence: 85%

See 1 more Smart Citation

A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching

Jain

Fell

Anand

2017

Procedings of the British Machine Vision Conference 2017

View full text Add to dashboard Cite

show abstract

“…The approach also suffers an increased time delay when the algorithm is attempting to generate accurate results for such discontinuous regions. An improvement to the poor quality of the disparity maps was achieved by Wang et al [94]. They used the AD-CT algorithm in the matching cost calculation stage with a semiglobal optimization framework on FPGA board.…”

Section: Global Approaches Several Global Methods Have Beenmentioning

confidence: 99%

Literature Survey on Stereo Vision Disparity Map Algorithms

2016

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This paper presents a literature survey on existing disparity map algorithms. It focuses on four main stages of processing as proposed by Scharstein and Szeliski in a taxonomy and evaluation of dense two-frame stereo correspondence algorithms performed in 2002. To assist future researchers in developing their own stereo matching algorithms, a summary of the existing algorithms developed for every stage of processing is also provided. The survey also notes the implementation of previous software-based and hardware-based algorithms. Generally, the main processing module for a software-based implementation uses only a central processing unit. By contrast, a hardware-based implementation requires one or more additional processors for its processing module, such as graphical processing unit or a field programmable gate array. This literature survey also presents a method of qualitative measurement that is widely used by researchers in the area of stereo vision disparity mappings.

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“…Each scanline by itself produces some streaking artifacts in the direction of the scanline, because the penalty values only favor persistence of previously optimal disparities along the scanline, but not in the reverse direction. Therefore, it is important not only to utilize several different scanlines like in [22], but also to have pairs of reverse scanlines to symmetrically offset the streaking. [10].…”

Section: Scanline Optimizationmentioning

confidence: 99%

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

Kenter

Schmitz

Plessl

2015

International Journal of Reconfigurable Computing

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FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

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Real-Time High-Quality Stereo Vision System in FPGA

Cited by 105 publications

References 20 publications

A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching

A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching

Literature Survey on Stereo Vision Disparity Map Algorithms

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

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