VLSI Signal Processing, IX
DOI: 10.1109/vlsisp.1996.558309
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Real-time MPEG-2 software decoding with a dual-issue RISC processor

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Cited by 8 publications
(1 citation statement)
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“…While [l I] [ll optimized], [12], and [13] require 704,504,450, and 520 instructions respectively, giving it a performance gain of more than four times over existing architectures. The main contriiutions to this performance gain are the Butterfly, and 128-bit Add-Sub instructions, which constitute nearly 40% of Fast IDCT computation.…”
Section: Performance Estimationmentioning
confidence: 99%
“…While [l I] [ll optimized], [12], and [13] require 704,504,450, and 520 instructions respectively, giving it a performance gain of more than four times over existing architectures. The main contriiutions to this performance gain are the Butterfly, and 128-bit Add-Sub instructions, which constitute nearly 40% of Fast IDCT computation.…”
Section: Performance Estimationmentioning
confidence: 99%