Real-time pedestrian detection on a xilinx zynq using the HOG algorithm

Low-Power Pedestrian Detection System on FPGA

“…Table 1 compares our implementation to the state-of-the-art. Regarding FPGA resources, our design is optimized for memory (what also affects energy) and therefore consumes the least memory resource except for the one in [9] which reports zero memory usage. The reason for this is that our pipeline works on every input pixel and there is not any buffer for input frames.…”

“…About DSPs usage, our design is the second optimized. The best one only uses four DSP blocks [9]. Concerning the number of flip-flops, our design uses quite a large number of FFs to fulfill the long pipeline.…”

“…With a negligible loss in accuracy, the best set of parameters provides a frame rate of 42.7 fps and high energy-efficiency of only 0.451 J/Frame. A detailed description of HOG implementation on FPGA is presented in [9], which achieves a high processing speed at 40 fps, with 1920 × 1080 input image size. Interestingly, in [10], HOG algorithm is analyzed on a heterogeneous system, including CPU, GPU, and FPGA.…”

HOG-AdaBoost Implementation for Human Detection Employing FPGA ALTERA DE2-115

“…To date, there are many papers on FPGA-based HOG that implemented in Xillix FPGA for high-speed and highaccuracy human detection systems [6][7][8][9][10]. In previous work [11], we have applied the FPGA-based human recognition in an image, we employed ALTERA DE2-115.…”

Efficient processing of vision kernels and deep neural networks on reconfigurable computing architectures

“…It also shows that our architecture P(16×16) outperforms other works by 3-46×, because it can compute one HOG cell in one clock cycle, but at the expense of resources. P(16×16) has resource usage overheads of 6.4×, 17×, and 32× for LUT, FF, and DSPs compared to the latest implementation in [79]. Our sequential architectures, P(8×8) and P(4×4), shows a compromise in terms of performance to reduce the resource usage overhead as shown in Table 3 In this work, we proposed a configurable hardware architecture for computing different histogrambased feature description algorithms.…”