Real-Time Scheduling on Multicore Platforms

Abstract

Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power problems impose limits on the performance of single-core designs. Accordingly, several chip manufacturers have already released, or will soon release, chips with dual cores, and it is predicted that chips with up to 32 cores will be available within a decade. To effectively use the available processing resources on multicore platforms, software designs should avoid co-executing applications or threads that can worsen the performance of shared caches, if not thrash them.While cache-aware scheduling techniques for such platforms have been proposed for throughput-oriented applications, to the best of our knowledge, no such work has targeted real-time applications. In this paper, we propose and evaluate a cache-aware Pfair-based scheduling scheme for real-time tasks on multicore platforms.

Parallel Real-Time Task Scheduling on Multicore Platforms

“…They showed that L2 contention can be reduced, and throughput improved, by discouraging threads that generate significant memory-to-L2 traffic from being co-scheduled. In recent work [1], we presented results comparable to those of Fedorova et al but pertaining to real-time systems. Specifically, we showed that it is possible to discourage high- * Work supported by a grant from Intel Corp. and by NSF grants CNS 0309825, CNS 0408996, and CCF 0541056.…”

“…There are several directions for future work. First, we want to combine this scheduling method with the methods in [1] so that both the "encouragement" and "discouragement" of co-scheduling can be supported in the same system. Second, we wish to include support for critical sections and precedence constraints in our work.…”

“…However, our method shows a substantial overall improvement with these task sets. Additionally, because an L2 miss incurs a time penalty up to two orders of magnitude greater than a hit, a relatively small miss-rate difference can impact performance significantly, as seen in [1].…”

Design and Implementation of Task Reprocessing on Medium-large Multi-core Architecture

“…Multi-core platform provides an environment to accomplish computation-intensive and complicated arithmetic real-time parallel issues. Multiprocessors proved that increasing the core count on a single die is the better solution than increasing processor clock frequencies (Where this idea suffers with power leakage issue [17], [14], [9]). Numerous single core issues need to be addressed and new approaches need to be advocated and evaluated on multi-core systems [15].…”

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches

“…Multi-core computing platforms can further aggravate the complexity of WCET analysis due to the possible inter-thread interferences in shared resources such as L2 caches, which are very difficult to analyze statically. While there have been recent studies on real-time scheduling for multi-core platforms Anderson et al 2006], all these studies basically assume that the worst-case performance of real-time threads is known. Therefore, it is a necessity to reasonably bound the WCET of real-time threads running on multi-core processors before the multi-core platforms can be safely employed by real-time systems.…”