Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures

Abstract

Abstract:The Hough Transform (HT) is a method for extracting straight lines from an edge image. The main limitations of the HT for usage in actual applications are computation time and storage requirements. This paper reports a hardware architecture for HT implementation on a Field Programmable Gate Array (FPGA) with parallelized voting procedure. The 2-dimensional accumulator array, namely the Hough space in parametric form (ρ, θ), for computing the strength of each line by a voting mechanism is mapped on a 1-dimensional array with regular increments of θ. Then, this Hough space is divided into a number of parallel parts. The computation of (ρ, θ) for the edge pixels and the voting procedure for straight-line determination are therefore executable in parallel. In addition, a synchronized initialization for the Hough space further increases the speed of straight-line detection, so that XGA video processing becomes possible. The designed prototype system has been synthesized on a DE4 platform with a Stratix-IV FPGA device. In the application of road-lane detection, the average processing speed of this HT implementation is 5.4 ms per XGA-frame at 200 MHz working frequency.

A Fast-Efficient parallel processing algorithm for straight line detection

“…The accuracy of the HT depends on accumulator cells and the bin size [20][21][22]. In this method, number of lines is calculated with maximum accuracy.…”

“…As shown in (2) represents number of PEs (Pn) required for the proposed method to detect the entire straight lines in the image with maximum resolution and 'n' is the number of rows of a n x n image. In earlier works, the angular resolution is taken as ∆θ = 1 0 [20][21][22].…”

“…Inter processor communication through reconfigurable mesh are required for the other methods. Also, the processors calculate cosine and sine values for different values of angles and perform arithmetic operations like addition and multiplication in the other methods [13][14][15][16][17][18][19][20][21][22]. The resolution of lines again can be increased by modifying edge detection method and increasing PEs.…”

FPGA Implementation of a Memory-Efficient Hough Parameter Space for the Detection of Lines

“…The execution time of this implementation would be dependant on the bandwidth and speed of the off-chip memory in use. Guan et al [8] created a system which applied the LHT to a video stream. They reduced the total memory requirements of the HPS, by setting the discretisation step of θ to 2 • (δ θ = 2 • ).…”

“…Hardware implementations, using Field Programmable Gate Arrays (FPGAs), have been investigated for their ability to accelerate the LHT through parallel processing. In [8], the authors implemented a high-speed parallel FPGA architecture capable of processing a video frame of 1024x768 pixels in 5.4ms. In [9], a low-latency LHT architecture for an image of 512x512 pixels is capable of applying the LHT in 1.07ms.…”