Real Time Video Processing on FPGA Using on the Fly Partial Reconfiguration

Bhandari, Sheetal U.; Subbaraman, Shaila; Pujari, Shashank; Mahajan, Rashmi

doi:10.1109/icsps.2009.32

Cited by 21 publications

(9 citation statements)

References 1 publication

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“…A complete initial bit stream must be generated, and then partial bit steams are generated for each reconfigurable module [3,12]. Figure 1 shows the design flow of module-based partial reconfiguration [9,12].…”

Section: Partial Reconfiguration Methodologymentioning

confidence: 99%

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

Vennila

Lakshminarayanan

2011

Circuits Syst Signal Process

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This paper presents a novel scalable and runtime dynamically reconfigurable FFT architecture for different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture for three different FFT points is realized using mixed radix-2 2 /2 3 /2 4 FFT algorithm in a modified Single-path Delay Feedback (SDF) pipelined architecture. Via a proper data flow reconfiguration it can support 64, 128 and 256. It can even be extended up to 8192-point transforms and uses only 13 butterfly units to realize 8192 points. This paper describes the implementation method of 256 and 128 point FFT, which is reconfigured partially from 64 point FFT. The whole system is implemented on a Xilinx XC2VP30 FPGA device. The implementation design addresses area efficiency and flexibility allowing the insertion of the partial modules dynamically to realize various FFT sizes. To verify the efficacy of this dynamic partial reconfigurable FFT design method, a conventional multiplexer based reconfigurable architecture was designed and tested on the same platform. Tested FPGA results for the Dynamic Partial Reconfigurable (DPR) method show the configuration time improvement and good area efficiency as compared to the reconfigurable architecture using conventional multiplexer techniques.

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Section: Partial Reconfiguration Methodologymentioning

confidence: 99%

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

Vennila

Lakshminarayanan

2011

Circuits Syst Signal Process

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“…The filter adapts to different user requirements at runtime. A realtime video processing system using PR is described in [Bhandari et al 2009], where different image processing filters are implemented in the same reconfigurable region to reduce resource requirements and power consumption. In [Birla and Vikram 2008], the AdaBoost algorithm for human detection is implemented on a Virtex-4 FPGA using PR.…”

Section: System Cost Reductionmentioning

confidence: 99%

“…Other such applications include using the same PR region to implement different stages of hardware cryptographic functions [Patterson 2000] and time multiplexing different stages of image/video processing [Bhandari et al 2009;Krill et al 2010]. In [Noguera and Kennedy 2007], the authors propose a method for power saving in networks by changing the implementation of the same function under different conditions.…”

Section: System Cost Reductionmentioning

confidence: 99%

FPGA Dynamic and Partial Reconfiguration

2018

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Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.

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“…As for filter/filterbank implementations using DPR, we note a 2D real filterbank based on the coefficient-only reconfiguration of a single 1D FIR Filter [5], a system that switches between a mean and a median filter via DPR [22], and a 3 × 3 2D FIR filter than can dynamically reconfigure its coefficients [23]. In [6], we implemented a real input, real coefficients 2D FIR filter by dynamically reconfiguring between the row and column filter.…”

Section: Background and Related Workmentioning

confidence: 99%

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

Llamocca

Pattichis

2014

VLSI Design

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We introduce a dynamically reconfigurable 2D filterbank that supports both real and complex-valued inputs, outputs, and filter coefficients. This general purpose filterbank allows for the efficient implementation of 2D filterbanks based on separable 2D FIR filters that support all possible combinations of input and output signals. The system relies on the use of dynamic reconfiguration of real/complex one-dimensional filters to minimize the required hardware resources. The system is demonstrated using an equiripple and a Gabor filterbank and the results using both real and complex-valued input images. We summarize the performance of the system in terms of the required processing times, energy, and accuracy.

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Real Time Video Processing on FPGA Using on the Fly Partial Reconfiguration

Cited by 21 publications

References 1 publication

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

FPGA Dynamic and Partial Reconfiguration

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

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