Realization of atomic layer etching of silicon

Athavale, Satish D.; Economou, Demetre J.

doi:10.1116/1.588651

Cited by 139 publications

(95 citation statements)

References 4 publications

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“…They also discussed introduction of structural damage in the top three silicon layers. In their experimental work 86 they used a helical resonator plasma source to achieve ALE of silicon by Cl 2 exposure and low energy Ar ion bombardment. They observed a self-limiting process with respect to both Cl 2 and ion dose, and concluded that control of the ion energy was the most important factor in realizing ALE.…”

Section: Iii-v: Gaasmentioning

confidence: 99%

“…The group of Economou performed both modeling 85 and experimental work 86 on Cl 2 /Ar + based ALE of silicon. Molecular dynamics simulations of Si ALE by Athavale et al 85 using 50 eV argon ion bombardment of Si(100) passivated with a monolayer of adsorbed chlorine showed that 93% of etched Si originated from the top silicon layer and 7% from the underlayer.…”

Section: Iii-v: Gaasmentioning

confidence: 99%

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Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

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The ability to achieve near-atomic precision in etching different materials when transferring lithographically defined templates is a requirement of increasing importance for nanoscale structure fabrication in the semiconductor and related industries. The use of ultra-thin gate dielectrics, ultra thin channels, and sub-20 nm film thicknesses in field effect transistors and other devices requires near-atomic scale etching control and selectivity. There is an emerging consensus that as critical dimensions approach the sub-10 nm scale, the need for an etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), has become essential, and that the more than 30-year quest to complement/replace continuous directional plasma etching (PE) methods for critical applications by a sequence of individual, self-limited surface reaction steps has reached a crucial stage. A key advantage of this approach relative to continuous PE is that it enables optimization of the individual steps with regard to reactant adsorption, self-limited etching, selectivity relative to other materials, and damage of critical surface layers. In this overview we present basic approaches to ALE of materials, discuss similarities/crucial differences relative to thermal and plasma-enhanced ALD, and then review selected results on ALE of materials aimed at pattern transfer. The overview concludes with a discussion of opportunities and challenges ahead. A requirement of increasing importance for nanoscale device fabrication is the ability to achieve atomic scale etching control and materials selectivity during pattern transfer.1-8 An etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), is expected to satisfy these needs as critical dimensions continue to shrink below the 10 nm scale.Demonstrations of self-limited dry etching methods capable of near-atomic resolution have a long history in the dry etching community and a brief review will be presented below. Key challenges for these approaches have been specialized equipment, long process times and low throughput.9,10 However, a recent demonstration using a commercial plasma etch tool 10 and activities within the dry etching community 11 provide indications that the situation has changed, and that we may have reached for ALE the Tipping Point which Gladwell defined as the "the moment of critical mass, the threshold, the boiling point" when "ideas and products and messages and behaviors spread like viruses do".12 This is due to several factors, including unprecedented demands on dry etching technology introduced by the semiconductor device evolution according to Moore's law that can be satisfied by atomic layer etching, advanced capabilities in plasma etch, and the existence of a critical level of information on plasma etch and ALD methods as applied in the semiconductor fabrication space.In this article we will provide a review of background of these approaches, and focus on issues that have to be overcome for widespread implement...

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Section: Iii-v: Gaasmentioning

confidence: 99%

Section: Iii-v: Gaasmentioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

View full text Add to dashboard Cite

show abstract

“…They presented experimental results in a follow up work in which they used a helicon plasma for generating the Ar + ions. 33 By applying and tuning a DC bias on the substrate, the Ar + ion bombardment energy could be adjusted to etch one monolayer off from silicon in an ∼100 s cycle. The process was self-limiting with respect to both chlorine dose and the ion dose while the etch rate was found to be a strong function of the DC bias on the substrate, i.e., the ion bombardment energy.…”

Section: The Early Days Of Atomic Layer Etchingmentioning

confidence: 99%

Atomic Layer Etching: What Can We Learn from Atomic Layer Deposition?

Faraz

Roozeboom

Knoops

et al. 2015

ECS J. Solid State Sci. Technol.

128

106

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Current trends in semiconductor device manufacturing impose extremely stringent requirements on nanoscale processing techniques, both in terms of accurately controlling material properties and in terms of precisely controlling nanometer dimensions. To take nanostructuring by dry etching to the next level, there is a fast growing interest in so-called atomic layer etching processes, which are considered the etching counterpart of atomic layer deposition processes. In this article, past research efforts are reviewed and the key defining characteristics of atomic layer etching are identified, such as cyclic step-wise processing, self-limiting surface chemistry, and repeated removal of atomic layers (not necessarily a full monolayer) of the material. Subsequently, further parallels are drawn with the more mature and mainstream technology of atomic layer deposition from which lessons and concepts are extracted that can be beneficial for advancing the field of atomic layer etching.

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“…Digital etch techniques have been proposed to etch Silicon and III-Vs [7]- [13]. In this approach, the two elemental components of etching, oxidation and oxide removal, are applied separately.…”

Section: A Novel Digital Etch Technique Formentioning

confidence: 99%

A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

Lin

Zhao

Antoniadis

et al. 2014

IEEE Electron Device Lett.

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Abstract-We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of lowpower O 2 plasma oxidation, followed by diluted H 2 SO 4 rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ∼0.9 nm/cycle. We illustrate the new process by fabricating L g = 60-nm selfaligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO 2 for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/µm (V ds = 0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at V ds = 0.05 and 0.5 V, respectively, and ON current of 326 µA/µm at I OFF = 100 nA/µm and V dd = 0.5 V.

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Realization of atomic layer etching of silicon

Cited by 139 publications

References 4 publications

Atomic Layer Etching at the Tipping Point: An Overview

Atomic Layer Etching at the Tipping Point: An Overview

Atomic Layer Etching: What Can We Learn from Atomic Layer Deposition?

A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

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