Realization of baseband signal processing for Beidou/GPS multi-mode receiver by FPGA

Zeng, Yongxi; Yu, Yanzhong; Liu, Lijian

doi:10.1109/iccsn.2017.8230234

Cited by 7 publications

(5 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally other FPGAs applications in this list includes Hardware-In-the-Loop (HIL) [34,1115,[1276][1277][1278][1279][1280][1281][1282], GPS (Global Positioning System) [1283][1284][1285][1286][1287][1288][1289][1290][1291][1292][1293][1294][1295][1296][1297][1298], Positron Emission Tomography (PET) , bioinformatics [1325][1326][1327][1328][1329][1330][1331][1332][1333][1334][1335][1336][1337][1338][1339][1340][1341][1342], fuzzy logic [1343][1344][1345][1346][1347]…”

Section: Other Applicationsmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

View full text Add to dashboard Cite

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

show abstract

Section: Other Applicationsmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

View full text Add to dashboard Cite

show abstract

“…Table II shows the state of the storage of eight data in address 0, in which x[0] to x [7] and y[0] to y [7] are both signed numbers of 12bit, and the storage state in other addresses is similar to this. [1] x [2] x [3] x [4] x [5] x [6] x [7] RAM2 After sampling, correlation operations are started, use Quartus II as software platform and Verilog HDL language. The adopted FPGA belongs to the series of CYCLONE IV, and the model is EP4CE15F23C8.…”

Section: The Implementation Of Correlation Operationsmentioning

confidence: 99%

“…In the third group, the sequence Y slide two to the right, at the same time, expands a data y[-1]=0,which is located in C [7], and expands a data y[-2]=0,which is located in C [6]. Multiply correspondingly again, that is, [6]y [4], x [7]y [5]. As shown in Fig.…”

Section: The Implementation Of Correlation Operationsmentioning

confidence: 99%

“…Its powerful ability to suppress noise makes it extremely widely used in the field of signal processing [1]. The main application fields include the signal processing of radar signal receiver [2], [3], accurate positioning by measuring the delay difference of the same signal, the synchronization of the communication system by correlation between the receiving sequence and the local sequence, the decision of the signal in the direct sequence spread spectrum communication and the restoration of the original signal, and the application of the GPS receiver [4].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Research on Digital Correlator Algorithm Based on FPGA

Sun¹,

Jun²,

Geng³

et al. 2019

IJCTE

View full text Add to dashboard Cite

This paper designs and implements a parallel correlation algorithm for ultra-long sequence in large-scale field programmable gate array (FPGA). The operation speed is 64 times faster than traditional algorithms. Combining multiple data values in one RAM address improves the efficiency and avoids the time consumption caused by reading data repeatedly. The multi-group multiply accumulator is used to calculate the data read according to certain rules, which fully utilizes the advantages of parallel operation in FPGA and reduces the operation time. This algorithm overcomes the shortcomings of the limit of the number of multipliers in the serial pipeline operation method, which can only perform correlation operations on short sequences, and makes up that the general parallel algorithm is more convenient only for the correlation operation of the two signals without relative sliding, but the sequential control is too complex when the two signals have relative sliding.

show abstract

“…Different from the ASIC architecture, FPGA has better flexibility. Reference [10] takes full advantage of the reconfigurable structure of FPGA. They proposed a BDS/GPS dual-mode GNSS receiver based on FPGA.…”

Section: Introductionmentioning

confidence: 99%

A Novel VLSI Architecture for Multi-Constellation and Multi-Frequency GNSS Acquisition Engine

Yang

Chen

2019

IEEE Access

View full text Add to dashboard Cite

This paper proposes a novel VLSI architecture of GNSS acquisition engine based on shorttime correlation combined with an FFT scheme. The architecture supports multi-constellation systems and multi-frequency satellite signals flexibly by the manner of time-division multiplexing. The supported signals include GPS, BDS, GLONASS, GALILEO, QZSS, IRNSS, and SBAS. Compared with other direct acquisition structures, the search efficiency of the acquisition engine is improved by using the IF playback structure. Based on the characteristics of L1C and B1C signal spread spectrum codes, an efficient generation method and the circuit structure of Legendre sequence which is compatible with L1C and B1C spread spectrum codes are proposed. It can effectively reduce the die area of the spread spectrum code generator and the generation time of the L1C/B1C spread spectrum code. Combining with the acquisition scheme adopted in this paper, the structure of the short-time correlators' array is optimized, and the maximum clock frequency of the acquisition engine is significantly improved. The acquisition engine proposed in this paper is implemented in a 55-nm CMOS technology. The system occupied a silicon area of 2.1 mm 2 and consumes only 72.02-mW power while realizing the maximum clock frequency at about 333.33 MHz.

show abstract

Realization of baseband signal processing for Beidou/GPS multi-mode receiver by FPGA

Cited by 7 publications

References 0 publications

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array Applications—A Scientometric Review

Research on Digital Correlator Algorithm Based on FPGA

A Novel VLSI Architecture for Multi-Constellation and Multi-Frequency GNSS Acquisition Engine

Contact Info

Product

Resources

About