Realization of deep-submicron MOSFETS by lateral etching

Brumester, R.; Winnerl, J.; Neppl, F.

doi:10.1016/0167-9317(91)90136-2

Cited by 9 publications

(7 citation statements)

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“…All these processes have the advantage of reducing the gate length without increasing the complexity of the lithography requirements. Studies have shown that resist trimming is both reproducible and uniform, and could be a viable technique for deep submicron device manufacturing (Baker et al, 2000;Burmester et al, 1991;Chung et al, 1988;Ono et al, 1995). It is worth noting that the etching is on the top-down direction of the feature, whereas the trimming is the etching on the lateral side of the device.…”

Section: Introductionmentioning

confidence: 98%

“…Similar techniques to reduce the linewidth of the masking materials have also been described as "photoresist ashing" (Chung et al, 1988), "oxide lateral etching" (Burmester et al, 1991), or "resist thinning" (Lee et al, 1997;Nakao et al, 2000;Ono et al, 1995), and have been successfully used to fabricate n-type metal-oxide-semiconductor field effect transistors (MOSFETs) with effective channel length as small as 40 nm using deep ultraviolet (DUV) lithography (Ono et al, 1995). All these processes have the advantage of reducing the gate length without increasing the complexity of the lithography requirements.…”

Section: Introductionmentioning

confidence: 98%

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Effect of halogen in high‐density oxygen plasmas on photoresist trimming

Sin

Chen

Loh³

et al. 2004

AIChE Journal

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Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 98%

Effect of halogen in high‐density oxygen plasmas on photoresist trimming

Sin

Chen

Loh³

et al. 2004

AIChE Journal

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“…For example, multiple patterning, 13 spacer patterning, 14,15 and cutting 16 have made it possible to reduce the pitch between patterns, whereas photoresist trimming, 17,18 hard mask trimming, 19 and capping layer 20 aim at reducing critical dimensions (CDs). In this work, we have considered using an amorphous carbon hard mask 21 capped by a thin silicon oxide layer 20,22 in order to maximize CD reduction by suppressing photoresist thickness limitations.…”

Section: Introductionmentioning

confidence: 99%

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Pauliac-Vaujour

Brianceau

Comboroure

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Both sub-22 nm architecture design optimization and reliable, low-cost process development represent major challenges toward nanoscale device fabrication. In order to address the second of these two issues, the authors have demonstrated that it is possible to overcome current tool and process lithography limitations using a capped carbon hard mask process, without dramatically increasing device fabrication costs, as only existing tools are used in this process. Starting from 50 nm patterns, 25 nm fully depleted silicon-on-insulator (FDSOI) transistors with good reliability and acceptable electrical behavior are obtained. This patterning solution may be applied to existing lithography processes (dry or immersion ArF lithography) in order to enhance current resolution capabilities. Moreover, the use of a capping layer enables to set free from photoresist thickness limitations, which are becoming increasingly critical for sub-22 nm feature patterning. Indeed, for such dimensions, photoresist thickness generally needs to be lower than 66 nm in order to avoid pattern collapse effects. This trend can lead to serious integration problems especially for the fabrication of thick stack device architectures. Therefore, in addition to improving current lithography processes, our strategy may also be useful for novel lithography processes such as extreme ultraviolet lithography or maskless lithography. The authors have also demonstrated that the capped carbon hard mask process could enable the patterning of sub-11 nm FDSOI gates, with a current best result close to 7 nm, starting from 30 nm photoresist patterns. Note that all etching steps of the process have been performed in the same etching chamber, which is a key point for meeting industrial requirements. These results show that it is possible to bypass tool and process lithography limitations to pattern sub-22 nm devices without dramatically increasing fabrication costs while maintaining lithography throughput. The authors have therefore shown that the capped carbon hard mask process could be a high-performance and low-cost industry-compatible solution for nanoscale device fabrication.

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“…The technique has been successfully employed to fabricate metal-oxide-semiconductor field-effect transistors (MOSFETs) with effective channel lengths as small as 40 nm using DUV lithography . Similar techniques to reduce the line width of the masking materials have also been described as photoresist ashing, , oxide lateral etching, or resist thinning ,, processes. All of these processes have the advantage of reducing the gate length without increasing the complexity of the lithography requirements.…”

Section: Introductionmentioning

confidence: 99%

Photoresist Trimming in Oxygen-Based High-Density Plasmas: Effect of HBr and Cl₂Addition to CF₄/O₂Mixtures

Sin

Chen

Loh³

et al. 2003

Ind. Eng. Chem. Res.

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The effects of HBr or Cl 2 addition to CF 4 /O 2 plasmas on resist trimming were examined. Because the reactivity of halogens on trimming decreases from F to Br and then to Cl, the addition of HBr and Cl 2 to CF 4 /O 2 decreases the trim rate. In contrast, the etch selectivity of the resist to the underlying polysilicon and the trim-rate uniformity are generally improved with the addition of enough HBr to CF 4 /O 2 , whereas addition of Cl 2 has the opposite effect in that it degrades the selectivity and uniformity. The constituents of the resist sidewall in different plasma etchants with HBr or Cl 2 gas added to CF 4 /O 2 were examined using angle-resolved XPS to study how the trim rate is influenced by the sidewall films formed during resist trimming. The XPS results showed that the films formed on the resist sidewall had different constituents and concentrations according to the plasma chemistry. CO x Br y F z and CO x Cl y F z films were formed on the resist sidewall during trimming with HBr/CF 4 /O 2 and Cl 2 /CF 4 /O 2 , respectively. The presence of halogen in the plasma affects the availability of the oxygen atom to the resist surface. A greater atomic concentration ratio of oxygen to carbon and a higher degree of halogenation of the films coincide with a higher trim rate.

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Realization of deep-submicron MOSFETS by lateral etching

Cited by 9 publications

References 0 publications

Effect of halogen in high‐density oxygen plasmas on photoresist trimming

Effect of halogen in high‐density oxygen plasmas on photoresist trimming

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Photoresist Trimming in Oxygen-Based High-Density Plasmas: Effect of HBr and Cl₂Addition to CF₄/O₂Mixtures

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Realization of deep-submicron MOSFETS by lateral etching

Cited by 9 publications

References 0 publications

Effect of halogen in high‐density oxygen plasmas on photoresist trimming

Effect of halogen in high‐density oxygen plasmas on photoresist trimming

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Photoresist Trimming in Oxygen-Based High-Density Plasmas: Effect of HBr and Cl2Addition to CF4/O2Mixtures

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Product

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Photoresist Trimming in Oxygen-Based High-Density Plasmas: Effect of HBr and Cl₂Addition to CF₄/O₂Mixtures