Although single dopant signatures have been observed at low temperature [1][2], the impact on transistor performance of a single dopant atom at room temperature is not yet well understood. Here, for the first time, we provide an in-depth understanding of single dopant influence on NMOSFETs characteristics by linking low and room temperature transport. We demonstrate that, for gate length of 30 nm and below (channel length down to 10 nm), the presence of a single dopant dramatically alters the subthreshold behaviour when the dopant is located in the middle of the channel. Moving the dopants away from the channel leads to enhanced variability above the threshold voltage V t .Introduction Variability of threshold voltage (V t ) is now widely recognized as one of the most critical challenges for the future CMOS technology nodes [3]. In Extremely Thin SOI (ETSOI) transistors the random fluctuations due to channel doping are suppressed and lead to record Avt [4][5]. Still ETSOI devices are obviously sensitive to dopant induced dispersion arising from extensions. For the first time we are able to identify the effect of a single or a few dopants coming from extension and demonstrate that these dopants strongly affect the room temperature transfer characteristics of ultra-scaled NMOSFET, regardless the extension architecture. Low temperature measurements are further used to spatially locate the dopants responsible for the alteration of the room temperature characteristics.Experimental set-up SOI devices with gate length and transistor width down to 20nm have been fabricated ( fig.1). For low temperature measurement purpose a SiO 2 /poly-Si gate stack has been implemented. Although it is conservative this gate stack does not have any influence on dopant configuration in the extensions. It specifically gives the lowest noise level as possible as compared to advanced high K/metal gate stack [6]. In addition a 5 nm thick thermal SiO 2 is used as gate dielectric so that gate leakage does not affect the differential conductance at low temperature (LT). For LT measurements, the devices are mounted in a dilution refrigerator (T min = 45mK). The drain source differential conductance G is directly measured by a lock-in amplifier detection. The AC drain voltage is 50 µV (linear regime) and a DC drain voltage is added to record the Coulomb diamonds, i.e. the 2D periodic plot of the conductance vs V d and V g .Results and discussion SOI devices with dopants scattered in the channel (A-type samples) -First measurements were performed on 20 nm thick SOI devices. In these devices As extensions were implanted right after gate etching. Kinetic Monte Carlo (KMC) process simulation enables the representation of stochastic processes (such as implantation and diffusion) in a device environment [7]. Fig.2 shows a simulated dopant configuration in which all thermal budgets during device fabrication are taken into account. We define the effective length L eff as the distance between two regions with continuous doping, i.e. doping level leading to...

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