Realization of DTMOS based CFTA and multiple input single output biquadratic filter application

Başak, Muhammed Emin

doi:10.1016/j.aeue.2019.04.027

Cited by 5 publications

(5 citation statements)

References 24 publications

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“…The topology of the proposed filter (Fig. 2) can be directly synthesized from the matrix (7). The filter consists of eight OTAs and two capacitors (both grounded).…”

Section: Design Proposalmentioning

confidence: 99%

“…Commonly proposed analogue frequency filters which provide several transfer functions [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11] have multiple inputs and/or outputs. Typical topologies (organization of inputs and outputs) are known as: Single-Input Multiple-Output (SIMO) filters [1], [2], [3], Multiple-Input Single-Output filters [4], [5], [6], [7], [8] and Multiple-Input Multiple-Output (MIMO) filters [9], [10], [11]. Specific type of the transfer function is then available based on the selection of input/output (or a suitable combination of inputs/outputs).…”

Section: Introductionmentioning

confidence: 99%

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Reconnection-Less Reconfigurable Filter Based on Method of Unknown Nodal Voltages Using 4×4 Matrix

Langhammer

Šotner

2023

IEEE Access

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The paper introduces a novel design solution of a reconnection-less reconfigurable filter based on the method of unknown nodal voltages (MUNV). The filter offers all standard 2 nd -order transfer functions and the electronic adjustment of the pole frequency and quality factor, which are mutually independent. The introduced design brings following advantages in comparison to other relevant solutions (MUNV-based reconnection-less reconfigurable filters): a) it consists of four independent nodes which brings the advantage of both working capacitors being grounded as floating capacitors can cause unpredictable parasitic behavior, b) the additional adjustment of the quality factor, c) the additional adjustment of the pass-band at lower and higher frequencies. Simulations and experimental measurements were carried out in order to verify the proposed design.

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“…The topology of the proposed filter (Fig. 2) can be directly synthesized from the matrix (7). The filter consists of eight OTAs and two capacitors (both grounded).…”

Section: Design Proposalmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reconnection-Less Reconfigurable Filter Based on Method of Unknown Nodal Voltages Using 4×4 Matrix

Langhammer

Šotner

2023

IEEE Access

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“…Bulk terminal and gate terminal of MOS transistor are connected together to reduce the threshold voltage of MOS transistor in this technique. By doing this, the power consumption of circuit is significantly decreased because of MOS transistor operating in subthreshold region [2,4,9,[11][12][13][14][15][16]21]. Figure 1 demonstrates the structure of DTMOS transistor and its symbol.…”

Section: Ota Structure Based On Dtmos Transistormentioning

confidence: 99%

“…Many methods in order to decrease the power dissipation of the circuit have been used by researchers [2][3][4][5][6][7][8][9][10][11][12]. One of the effective methods called DTMOS technique is utilized to reduce the power consumption and the required supply voltages [2,4,9,[11][12][13][14][15]. In this technique, bulk terminal is connected to gate terminal of MOS transistor so that the power dissipation becomes noteworthily less compared to the designs using traditional MOS transistors.…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage and Low-Power Analog Multiplier/Divider Using OTA Based on DTMOS Transistor

Yildirim¹

2021

Deu Muhendislik Fakultesi Fen Ve Muhendislik

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A low-voltage and low-power current mode analog multiplier/divider design is presented in this paper. The multiplier/divider is based on operational transconductance amplifier (OTA) utilizing dynamic threshold MOS (DTMOS) structure and consists of only three OTAs. The circuit has the ability of consuming low power and requiring low voltage power supplies. 0.13µm IBM CMOS technology parameters are used to simulate the suggested multiplier/divider design and the simulation results are obtained using LTspice program. The current mode analog multiplier/divider architecture consumes only 12.07nW and requires ±0.2V of supply voltages thanks to employing DTMOS transistor. The simulation results agree well with the expected results.

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“…Figure 6. DTMOS transistor and its circuit symbol[39].The simulation results have been obtained utilizing the SPICE program, employing 0.13 µm IBM CMOS technology parameters. The power supply and bias voltage were chosen as VDD = −VSS = 0.6 V and VB = −0.2 V, respectively.…”

mentioning

confidence: 99%

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

Vahbeh,

Özer,

Kaçar

2024

Electronics

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In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

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Realization of DTMOS based CFTA and multiple input single output biquadratic filter application

Cited by 5 publications

References 24 publications

Reconnection-Less Reconfigurable Filter Based on Method of Unknown Nodal Voltages Using 4×4 Matrix

Reconnection-Less Reconfigurable Filter Based on Method of Unknown Nodal Voltages Using 4×4 Matrix

Low-Voltage and Low-Power Analog Multiplier/Divider Using OTA Based on DTMOS Transistor

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

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