Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

Pelard, C.; Gebara, E.; Kim, A.J.; Vrazel, M.; Bien, Franklin; Hur, Y.; Maeng, M.; Chandramouli, S.; Chun, C.; Bajekal, Sanjay; Ralph, Stephen E.; Schmukler, Bruce C.; Hietala, V.M.; Laskar, J.

doi:10.1109/jssc.2004.833569

Cited by 61 publications

(21 citation statements)

References 8 publications

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“…The precise delays between taps can be generated by lumped LC structures that absorb the parasitic capacitance of the output driver [4]. Alternatively, the taps can be generated using a variable delay line that references its delay to the period of the data signal, such as in the receiver equalizer proposed in [5].…”

Section: Introductionmentioning

confidence: 99%

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing

Bichan

Carusone

2008

2008 IEEE Custom Integrated Circuits Conference

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This paper presents a 6.5 Gb/s transmitter for use in backplane links. This transmitter incorporates a finite impulse response filter with programmable tap spacing in the output driver to compensate for intersymbol interference. Using jitter-minimizing tap weights computed using a behavioral model of the transmitter, it is shown that at 6.5 Gb/s peak-to-peak data-dependent jitter is reduced by over 50% by using a tap spacing of 0.53 unit intervals (UI) instead of the usual 1 UI.

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Section: Introductionmentioning

confidence: 99%

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing

Bichan

Carusone

2008

2008 IEEE Custom Integrated Circuits Conference

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“…The rms value CIJ, , is determined from the pdf in (9). The rms value is useful for determining the timing margins that will achieve a particular BER [13].…”

Section: A 2-pammentioning

confidence: 99%

Cancellation of Crosstalk-Induced Jitter

Buckwalter

Hajimiri

2006

IEEE J. Solid-State Circuits

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Abstract-A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre-or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10 12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps.

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“…The impairments include the frequency-dependent loss characteristics of the copper channels and the interference from the adjacent channels, known as Crosstalk [3]. Moreover, the presence of the open-ended vias at the thick backplane intercard as well as channel discontinuities between the intercards induce reflections which further degrade the signal integrity [4].To improve the data transmission quality, the TX and RX equalization has been employed to remove the intersymbol interference (ISI) resulting from the finite channel bandwidth and reflections caused by a non-ideal channel. The incorporation of a decision-feedback equalization (DFE) scheme in the RX and a feed-forward equalization (FFE) scheme in the TX allows much more reliable NRZ (bi-level) data transmission at multi-GHz, and thus relieves the need for multi-level data transmission which demands higher design complexity and power consumption for the transceiver [2][5] [6].…”

mentioning

confidence: 99%

Testable Design for Advanced Serial-Link Transceivers

Lin

Cheng

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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This paper describes a DfT solution for modern seriallink transceivers. We first summarize the architectures of the Crosstalk Canceller and the Equalizer used in advanced transceivers to which the proposed solution can be applied. The solution addresses the testability and observability issues of the transceiver for both characterization and production testing. Without using sophisticated testing instrument setting, the proposed solution could test the clock and data recovery circuit and characterize the decision-feedback equalizer in the receiver. Our experiments demonstrate that the proposed method has significant higher fault coverage and lower hardware requirement than the conventional approach of probing the eyeopening of the signals inside the transceiver. IntroductionImproved fabrication technology enables the continuing increase of both on-chip operational speed and the data rate of inter-chip communications. Modern serial links maximize the interconnect performance by employing high fanin multiplexing transmitters (TX) and high fan-out demultiplexing receivers (RX). Industry standards [1] for specifications of I/O electrical characteristics of 6+ to 11+ Gb/s interfaces have been developed, which target various applications in optical modules, high-speed backplanes, and chip-to-chip interconnect [2]. The long-range backplane applications are particularly challenging for robust high-speed I/O due to the combined effects of the physical impediments in legacy backplane channels. The impairments include the frequency-dependent loss characteristics of the copper channels and the interference from the adjacent channels, known as Crosstalk [3]. Moreover, the presence of the open-ended vias at the thick backplane intercard as well as channel discontinuities between the intercards induce reflections which further degrade the signal integrity [4].To improve the data transmission quality, the TX and RX equalization has been employed to remove the intersymbol interference (ISI) resulting from the finite channel bandwidth and reflections caused by a non-ideal channel. The incorporation of a decision-feedback equalization (DFE) scheme in the RX and a feed-forward equalization (FFE) scheme in the TX allows much more reliable NRZ (bi-level) data transmission at multi-GHz, and thus relieves the need for multi-level data transmission which demands higher design complexity and power consumption for the transceiver [2][5] [6]. Meanwhile, crosstalk (XTalk) which is the dominant noise for microstrip interconnects is becoming a limiting factor for signal integrity. Among various types of XTalk sources, the near-end crosstalk (NEXT) is the most severe one [8]. Active NEXT cancellation in the transceiver could be an effective solution to addressing the XTalk problem [3] [4]. Figure 1 illustrates the architecture of an advanced transceiver which includes a Clock and Data Recovery circuit (CDR) and a DFE in the RX, a FFE in the TX, and a XTalk Canceller between the TX and RX. This transceiver has the capability to equalize the loss...

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Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

Cited by 61 publications

References 8 publications

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing

Cancellation of Crosstalk-Induced Jitter

Testable Design for Advanced Serial-Link Transceivers

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