Recent Advances in Analog, Mixed-Signal, and RF Testing

Abstract

Due to the lack of widely applicable fault models, testing for analog, mixedsignal (AMS), and radio frequency (RF) circuits has been, and will continue to be, primarily based on checking their conformance to the specifications. However, with the higher level of integration and increased diversity of specifications for measurement, specification-based testing is becoming increasingly difficult and costly. As a result, design for testability (DfT), combined with automatic test stimuli generation, has gradually become a necessity to ensure test quality at an affordable cost. This paper provides an overview of cost-effective test techniques that either enhance circuit testability, or enable built-in self-test (BIST) for integrated AMS/RF frontends. In addition, we introduce several low-cost testing paradigms including the loopback testing, alternate testing, and digitally-assisted testing that offer the promise of significant test cost reduction with little or even no compromise in test quality. Moving forward, in addition to screening the defective parts, testing will play an increasingly important role in supporting other post-silicon quality assurance functions such as post-silicon validation, tuning, and in-field reliability of system chips.

Digital-Compatible Testing Scheme for Operational Amplifier

“…In contrast, a larger value of C COUNT_FAIL , which is related to a reduction of Δ SR , can be given by (8).…”

“…Similarly, the counting numbers are rounded to be 97 by (7) for Δ SR 0 0.5 and 291 by (8) for Δ SR 0 0.5, respectively. The three conditions, i.e.…”

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

“…In practice, the error term ε t,m models the variation component that is spatially uncorrelated and, hence, cannot be captured by the DCT basis functions in (1). BMF aims to accurately find the DCT coefficients {α t,m,k ; k = 1, 2, ..., K} by measuring very few dies {(x (n) , y (n) , g t,m (n) ); n = 1, 2, ..., N} from the m-th wafer, where (x (n) , y (n) ) and g t,m…”

“…Today, a typical system on chip (SOC) is composed of numerous analog/RF and digital circuit blocks. Testing the analog/RF circuits within a complex SOC is extremely expensive and may even dominate the overall test cost [1]- [2]. For this reason, reducing the test cost for analog/RF circuits is one of the grand challenges for the test community.…”

Test cost reduction through performance prediction using virtual probe

“…In particular, testing mixed-signal and RF components in a system on chip (SOC) to examine their conformance to specifications [1] could account for up to 70% of the overall test cost of a mixed-signal SoC [2]. In addition to random defects and systematic failures that could result in defective devices, parametric variations in circuit/device/process parameters (such as gate length, dopant concentration, and metal thickness) cause deviations in device performances (such as gain, power, and bandwidth) and, hence, also lead to yield loss.…”