Recent advances in nanoparticle memories

Photoconductivity of Langmuir−Blodgett Monolayers of Silicon Nanoparticles

“…A variety of physical and chemical approaches have been reported for the preparation of silicon nanoparticles, including ion implantation, 11,12 thermal vaporization, 13 laser ablation, 14,15 gas phase decomposition of silanes based on low-pressure nonthermal plasmon, 16 electrochemical etching by pulse anodization, 17 and electroreductive synthesis. 18,19 Notably, solution chemistry routes have also been reported which offer the striking advantages of ready manipulation of the particle dimensions and surface chemical functionalization.…”

Silicon Oxide Films Containing Amorphous or Crystalline Silicon Nanodots for Device Applications

“…They use processes of direct charge tunnelling to the nanocrystals, FowlerNordheim tunnelling or channel hot electron (CHE) injection. The result is capturing of one or a few electrons in a potential well with well defined spatial position (Tsoukalas et al, 2005). The captured electron controls the current through a conducting channel situated close to the position of the captured electron and thus the nanocrystal plays the role of a floating gate.…”

“…An important advantage of the NVMs containing NCs is that they have shown a superior endurance at increased temperatures than the standard polysilicon floating gate NVMs and those using charge storage in natural traps. More detailed information on the principles of operation and non-volatile memories containing semiconductor or metal nanoparticles in various matrices can be found in a number of recent reviews [see for example (Horváth&Basa, 2009;Steimle et al, 2007;Tsoukalas et al, 2005).…”

“…The insulator of such MIS structure normally consists of three layers (Dimitrakis et al, 2005;Tiwari et al, 1996;Tsoi et al, 2005): (i) ultra thin tunnel SiO 2 layer grown on the crystalline Si wafer followed by (ii) composite layer of Si nanocrystals (NCs) in a SiO 2 matrix (nc-Si-SiO 2 ) and (iii) control SiO 2 layer, which insulates the NCs from the control gate. The middle nc-Si-SiO 2 layer has been mostly prepared by ion implantation of Si in thermal SiO 2 and subsequent annealing at high temperature ( 900 0 ) (Normand et al, 2004 and references therein;Carreras et al, 2005;Ng et al, 2006a), by applying some chemical vapor deposition (CVD) technique for Si nanocrystals fabrication and subsequent CVD deposition of silicon dioxide (Lombardo et al, 2004;Oda et al, 2005;Rao et al, 2004), by deposition of a ultra thin amorphous Si layer and a subsequent oxidation of this layer at a high temperature (Kouvatsos et al, 2003;Tsoi et al, 2005) or by thermal evaporation of SiO powder under selected oxygen pressure (Lu et al, 2005(Lu et al, , 2006.…”

“…It has been demonstrated that the application of low-energy ion beam implantation has resulted in preparation of very promising NVMs with Si nanocrystals (Horváth&Basa, 2009;Tsoukalas et al, 2005) since it allows (Normand et al, 1998) to avoid wide distribution of NCs through the oxide layer and to obtain NCs at a specific location into the host matrix. It has been demonstrated that memory cells fabricated following a procedure including implantation with 1 keV silicon ions to a dose of 2×10 16 cm −2 and subsequent annealing at 950 0 C for 30 min in N 2 + 1.5% O 2 (Normand et al, 2003;Tsoukalas et al, 2005) displayed more than 10 6 write/erase ± 9 V/10 ms cycles without observation of gate degradation.…”