Recent progress in low-temperature-process monolithic three dimension technology

Abstract

Monolithic three-dimension (3D) integration is an ultimate alternative method of fabricating high density, high performance, and multi-functional integrated circuits. It offers the promise of being a new approach to increase system performance. How to manage the thermal impact of multitiered processes, such as dopant activation, source/drain silicidation, and channel formation, and to prevent the degradation of pre-existing devices/circuits become key challenges. In this paper, we provide updates on several important monolithic 3D works, particularly in sequentially stackable channels, and our recent achievements in monolithic 3D integrated circuit (3D-IC). These results indicate that the advanced 3D architecture with novel design tools enables ultrahigh-density stackable circuits to have superior performance and low power consumption for future artificial intelligence (AI) and internet of things (IoTs) application.

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

“…Ultra-thin-body (UTB) silicon in an insulator (SOI) configuration has been widely studied and adopted in our previous works [ 26 , 27 , 28 , 29 ] for its outstanding electrostatics due to excellent suppression of the short channel effects (SCEs). However, it is still hard to thoroughly remove the interface traps and fixed oxide defects in back oxide which inevitably degrade the device performance [ 30 , 31 ].…”

Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

“…Significant work has been done on the monolithic 3D IC design in recent times, most of which contributed to developing various design concepts of 3D ICs. The studies in this field include developing a face-to-face stacked heterogeneous 3D IC structure [13], exploring various microfluidic cooling mechanisms for 3D ICs [14], studying recent developments in monolithic 3D ICs and the high density and performance benefits [15], designing a logic-on-memory processor using monolithic 3D (M3D) IC techniques [16], developing a design and testing system for M3D ICs [17], comparing the TSV-based 3D structure with M3Ds [18,19], studying the effect of process variation on the performance of M3D ICs [20,21], and developing effective gate-sizing methods to boost circuit speed while considering intra-die process variation [22]. Other related studies include repurposing various components of commercial 2D P&R tools to implement 3D ICs [23][24][25][26].…”

Source/Drain Activation for Flexible Poly-Si Nanoscale pFETs with a Laser-Buffer Layer by CO2 laser Annealing

“…11 On the contrary, the light reflectivity of TiN approaches 100% in the far-infrared wavelengths regime successfully demonstrates the S/D dopant activation of nano-FET by CO 2 laser (λ = 10.6 μm). 12 Semiconductors are readily heated up during CO 2 laser illumination because the laser light, which has a photon energy of ∼0.117 eV, 13,14 can be effectively absorbed via free carrier excitation. 15,16 Similarly, the PI substrate is highly susceptive to the absorption of far-infrared laser.…”