Recent trends in embedded system software performance estimation

Patel, Ravindra; Rajawat, Arvind

doi:10.1007/s10617-013-9125-2

Cited by 8 publications

(6 citation statements)

References 9 publications

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“…A comprehensive overview from Patel and Rajawat with a focus on performance estimation can be found in [9]. According to their taxonomy our SBE framework can be classified as a combination of an analytical methodology and a simulation-based approach.…”

Section: Related Workmentioning

confidence: 99%

Performance estimation of streaming applications for hierarchical MPSoCs

Flasskamp

Sievers

et al. 2016

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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Parallel programming and effective partitioning of applications for embedded many-core architectures requires optimization algorithms. However, these algorithms have to quickly evaluate thousands of different partitions. We present a fast performance estimator embedded in a parallelizing compiler for streaming applications. The estimator combines a single execution-based simulation and an analytic approach. Experimental results demonstrate that the estimator has a mean error of 2.6% and computes its estimation 2848 times faster compared to a cycle accurate simulator.

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Section: Related Workmentioning

confidence: 99%

Performance estimation of streaming applications for hierarchical MPSoCs

Flasskamp

Sievers

et al. 2016

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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“…Currently, the program performance assessment methods can be classified into two categories: simulation based one and analysis model based one [5]. Mathematically the methods can also classified into linear and nonlinear assessments respectively, while the simulation methods are classified into instruction based and others.…”

Section: Related Workmentioning

confidence: 99%

Research on Program Execution Time Assessment of LLVM IR Program

Liu

Sun

et al. 2015

2015 Eighth International Conference on Internet Computing for Science and Engineering (ICICSE)

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Program performance assessment is one of important methods to optimize a system design. The assessment of program execution time is always key topic in computer structure. A good assessment can provide important measure basis for hardware/software automatic partitioning in reconfigurable computer compiler. This paper analyzes the characteristics of IR program and proposes an IR layer program classification algorithm for assessing the program execution time. The method can provide an accurate measure and can be constructed into a BP neural network assessment system. The experimental results show that the proposed assessment model has lower assessment deviation compared to other models under the same conditions. The BP neural network model can be trained.

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“…Simulation based estimation techniques can be classified into 3 main categories, namely instruction set simulator based (ISSB), native execution based (NEB) and virtual platform based (VPB) simulation [42]. NEB methods can be further classified as binary(assembly) level, intermediate representation (IR) level (e.g.…”

Section: Design Methodologies For Csoc Customizationmentioning

confidence: 99%

“…Thus, performance evaluation is introduced early in the design cycle. Patel et al discuss directions for embedded processor performance estimation and their salient features [42]. In this work, performance estimation techniques for embedded processors are grouped into two main categories namely, analytical models and simulation.…”

Section: Software Performance Estimationmentioning

confidence: 99%

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Automating FPGA-based CSoC platform generation

Wijesundera¹,

Senelie²

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Field Programmable Gate Array (FPGA) based configurable system-on-chip (CSoC) platforms have become a preferred choice for embedded computing systems to meet the increasing demand for shorter time-to-market (TTM) and lower non-recurring engineering (NRE) costs, due to both high density and myriad of on-chip hardware and software compute resources. However, the inability of existing tools to effectively exploit these resources to satisfy design constraints, especially from high level specifications such as C/C++, remains a bottleneck for meeting the TTM pressures. In this research, techniques for the automatic generation of a FPGA-based CSoC platform have been proposed to satisfy the area-time design constraints by taking user preferences into account. application specific FPGA-based CSoC has made it possible to facilitate the rapid design space exploration of complex applications without violating the stringent TTM requirements.ASICs provide the optimal configuration based on the requirements for performance, area or power for a given application but incur long TTM and high NRE cost.In contrast, FPGAs provide configurability and flexibility with shorter TTM and low NRE cost, even though the performance is comparatively low. For example, FPGAs typically reach the production stage within 3 − 5 months, whereas ASICs require support both soft and hard core embedded processors and is intended to be scalable to different embedded processor architectures.Hardware Area-Time Estimation: A reliable technique for hardware area-time estimation of applications on FPGAs. The technique is intended to have the ability to support different FPGA vendors and device families.Hardware-Software Partitioning: Novel technique for optimal partitioning of an application between hardware and software components of the FPGA-based CSoC while taking into account their complex data-dependencies.Soft Core Processor Subsetting: Rapid and reliable techniques for instruction subsetting for soft core processor customization, in order to minimize area utilization. The saved area can be deployed to port additional portions of the application into hardware for further performance improvement.Intelligent Framework for CSoC Platform Generation: Framework to generate application-specific FPGA-based CSoC platforms that achieves the best performance under user-specified area constraints. The framework is intended to recommend the best partitioning of the components of the application between hardware and software as well as the most appropriate processor (subsetted in the case of a soft core). OrganizationThe rest of the thesis is organized is as follows.• Chapter 2 presents an extensive discussion on existing literature. It initially discusses the available embedded computing architectures. A comparison of the advantages and limitations of the architectures moves the focus to CSoCs. Next,

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Recent trends in embedded system software performance estimation

Cited by 8 publications

References 9 publications

Performance estimation of streaming applications for hierarchical MPSoCs

Performance estimation of streaming applications for hierarchical MPSoCs

Research on Program Execution Time Assessment of LLVM IR Program

Automating FPGA-based CSoC platform generation

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