Recognizing Speed Limit Sign Numbers by Evolvable Hardware

Tørresen, Jim; Bakke, J.W.; Sekanina, Lukáš

doi:10.1007/978-3-540-30217-9_69

Cited by 11 publications

(3 citation statements)

References 9 publications

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“…A specialized architecture has been proposed by Torresen to evolve prosthetic hand controller [26] and sign number recognizer [28]. The idea of incremental evolution has been applied to find configurations of subsystems of that architecture.…”

Section: Incremental Evolutionmentioning

confidence: 99%

Evolutionary Design of Digital Circuits: Where Are Current Limits?

Sekanina

2006

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)

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The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and innovation that can be obtained by means of these approaches. In particular, gate-level evolution, circuit evolution in PLAs, functional-level evolution, incremental evolution, evolution utilizing developmental schemes and some application-specific schemes are analyzed. It is shown that we are able to effectively explore the search spaces not much larger than 2 1000 points and that the innovative solutions can be produced independently of the utilized method.

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Section: Incremental Evolutionmentioning

confidence: 99%

Evolutionary Design of Digital Circuits: Where Are Current Limits?

Sekanina

2006

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)

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“…Classify the bit array using a classifier system. To classify the number given by the 7 x 5 bit array, we have got a high detection rate both with a feed-forward neural network trained by the backpropagation algorithm [11] as well as classification by evolvable hardware [12]. The experiments have so far been based on single images.…”

Section: Sign Number Recognitionmentioning

confidence: 99%

Efficient image filtering and information reduction in reconfigurable logic

Tørresen¹,

Bakke²,

Sekanina³

Proceedings Norchip Conference, 2004.

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An automatic sign detection system could be important in enhancing traffic safety. Such a system would have to be able to provide high speed processing in its real-time environment. In this paper, we show how one of the time consuming parts of a speed limit detection algorithm can be implemented in reconfigurable logic to speed up the processing. Results indicate that the present system would be able to handle 12 images per second.

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“…An early version of the system (with few results) was introduced in [5]. Results from our experiments with sign number classification in evolvable hardware are given in [6]. We have found very little work on speed limit sign classification.…”

Section: Introductionmentioning

confidence: 99%