Reconciling Time Predictability and Performance in Future Computing Systems

Cazorla, Francisco J.; Abella, Jaume; Mezzetti, Enrico; Hernández, Carles; Vardanega, Tullio; Bernat, Guillem

doi:10.1109/mdat.2017.2766558

Cited by 4 publications

(4 citation statements)

References 9 publications

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“…The accelerator should ensure timing compositional property, which means that any global worst case execution time (WCET) is composed of local WCETs. This also implies that the WCET in a core experiencing resources conflicts, e.g., accesses to the memory hierarchy, is safely approximated by adding the resource interference times to the WCET on the core executing without interferences [66]. The timing compositional property requires in-order instruction pipeline and is compatible with caches, provided they have an LRU replacement policy.…”

Section: High-performance Computation Platformsmentioning

confidence: 99%

Recent Advances and Trends in On-Board Embedded and Networked Automotive Systems

Bello

Mariani²,

Mubeen

et al. 2019

IEEE Trans. Ind. Inf.

135

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Modern cars consist of a number of complex embedded and networked systems with steadily increasing requirements in terms of processing and communication resources. Novel automotive applications, such as automated driving, rise new needs and novel design challenges that cover a broad range of hardware/software engineering aspects. In this context, this paper provides an overview of the current technological challenges in onboard and networked automotive systems. This paper encompasses both the state-of-theart design strategies and the upcoming hardware/software solutions for the next generation of automotive systems, with a special focus on embedded and networked technologies. In particular, this paper surveys current solutions and future trends on models and languages for automotive software development, on-board computational platforms, in-car network architectures and communication protocols, and novel design strategies for cybersecurity and functional safety.

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Section: High-performance Computation Platformsmentioning

confidence: 99%

Recent Advances and Trends in On-Board Embedded and Networked Automotive Systems

Bello

Mariani²,

Mubeen

et al. 2019

IEEE Trans. Ind. Inf.

135

View full text Add to dashboard Cite

show abstract

“…In particular, a more powerful set of WCET-aware monitors (performance monitoring counters) helps to provide insightful information on application worst-case behavior when run on the target hardware as an instrumental element to build a safety argument 12 . On the timing analysis side, the use of statistical-based approaches is on the rise as it fits the increasing execution-time variability applications suffer when running on complex processors such as GPUs [3][4] .…”

Section: Time Predictabilitymentioning

confidence: 99%

Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain

et al. 2018

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GPUs have been shown to cover the computing performance needs of autonomous driving (AD) systems. However, since the GPUs used for AD build on designs for the mainstream market, they may lack fundamental properties for correct operation under automotive's safety regulations. In this paper, we analyze some of the main challenges in hardware and software design to embrace GPUs as the reference computing solution for AD, with emphasis in ISO 26262 functional safety requirements.

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“…Performance-improving features, until recently only used in processors for the high-performance domain, are increasingly used in processors in domains like automotive [14]. Those features include multicores, multi-level caches, complex onchip networks, and accelerators, among which GPUs have a dominant position [4], [35], [27].…”

Section: Introductionmentioning

confidence: 99%

On the reliability of hardware event monitors in MPSoCs for critical domains

Barrera

Kosmidis

Tabani

et al. 2020

Proceedings of the 35th Annual ACM Symposium on Applied Computing

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Performance Monitoring Units (PMUs) are at the heart of most-advanced timing analysis techniques to control and bound the impact of contention in Commercial Off-The-Shelf (COTS) SoCs with shared resources (e.g. GPUs and multicore CPUs). In this paper, we report discrepancies on the values obtained from the PMU event monitors and the number of events expected based on PMU event description in the processor's official documentation. Discrepancies, which may be either due to actual errors or inaccurate specifications, make PMU readings unreliable. This is particularly problematic in consideration of the critical role played by event monitors for timing analysis in domains such as automotive and avionics. This paper proposes a systematic procedure for event monitor validation. We apply it to validate event monitors in the NVIDIA Xavier and TX2, and the Zynq UltraScale+ MPSoC. We show that, while some event monitors count as expected, this is not the case for others whose discrepancies with expected values we analyze.

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Reconciling Time Predictability and Performance in Future Computing Systems

Cited by 4 publications

References 9 publications

Recent Advances and Trends in On-Board Embedded and Networked Automotive Systems

Recent Advances and Trends in On-Board Embedded and Networked Automotive Systems

Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain

On the reliability of hardware event monitors in MPSoCs for critical domains

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