Reconfigurable Address Generators for Stream-Based Computation Implemented on FPGAs

Vistnes, K.E.; Soeraasen, O.

doi:10.1109/ipdps.2005.374

Cited by 2 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many methods for multiple accesses to memory for parallel and distributed operations of an algorithm have been reported. [26][27][28][29][30][31][32][33][34][35][36][37] In our work, a data management unit (DMU) is used to schedule all requests for transferring data between the FIFO buffers and on-chip memory. The DMU consists mainly of multiple address generation units (AGUs) used to control reading and writing access to on-chip memory.…”

Section: Data Management Unitmentioning

confidence: 99%

See 1 more Smart Citation

Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

Liu

Wyrwicz

2018

Review of Scientific Instruments

View full text Add to dashboard Cite

We report the design and implementation of a parallel two-dimensional fast Fourier transform (2D FFT) algorithm on a Field Programmable Gate Array (FPGA) for real-time MR image processing. Although a number of architectures of 2D FFT hardware processors have been reported, these generic processors or IP cores are not always effective for processing MRI data. The key feature of our design is that our processors are customized solely for real-time MRI applications. We demonstrate that by considering the unique features of real-time MRI data streams, we were able to develop and implement the 2D FFT processors that are resource-efficient and flexible enough to handle both regular and irregular data. Using a data-driven approach, we were able to simplify the inter-processor data communication while maintaining data synchronization without a synchronous clock signal bus and complex interconnection network. We experimentally verified our designs by processing multi-slice image data sets with 128 × 128 and 256 × 256 in-plane resolution. The results demonstrate the effectiveness of our 2D FFT processors and show that image reconstruction can be accelerated in proportion to the parallel processing factor. We achieved image-reconstruction processing rates up to 3000 and 800 slices per second for images with 128 × 128 and 256 × 256 in-plane resolution, respectively. The results also indicate that the image-reconstruction acceleration is primarily limited by the speed of the data transfer between the FPGA device and external sensors.

show abstract

Section: Data Management Unitmentioning

confidence: 99%

“…In our design, we greatly simplified the data synchronization by using a data-driven approach. 27,28 In data-driven processes, no operation instructions are required because the execution of an algorithm is predefined. All non-arithmetic operations are moved forward as long as their input data elements (operands) are available.…”

Section: Data Management Unitmentioning

confidence: 99%

Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

Liu

Wyrwicz

2018

Review of Scientific Instruments

View full text Add to dashboard Cite

show abstract

“…Vistnes and Søråsen's stream generator [8] creates regular, periodic patterns of addresses independently of the main processor. Using these patterns, the generator can access rectangular matrix structures with up to three dimensions.…”

Section: Related Workmentioning

confidence: 99%

“…The address engine uses the alternate integer representation [8] to map matrix coordinates to a linear address space:…”

Section: Data Address Enginementioning

confidence: 99%

An Event-Assisted Sequencer to Accelerate Matrix Algorithms

Burdeniuk

Lim

et al. 2010

2010 Fifth IEEE International Symposium on Electronic Design, Test &Amp; Applications

View full text Add to dashboard Cite

This paper presents a sequencer that accelerates matrix algorithms arising naturally in many multimedia and signal processing applications. The accelerator has been designed to carry out data management tasks common to these algorithms. A novel event-based parameter update mechanism allows production of continuously varying patterns to access triangular, banded and other irregular matrix structures. It has been verified that the accelerator significantly reduces the workload of the attached CPU for a wide range of algorithms. The accelerator has been implemented on a Virtex-5 FPGA platform where it required 1856 slices and achieved a post place-and-route speed of 64 MHz.

show abstract

Reconfigurable Address Generators for Stream-Based Computation Implemented on FPGAs

Abstract: Abstract

Cited by 2 publications

References 6 publications

Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

An Event-Assisted Sequencer to Accelerate Matrix Algorithms

Contact Info

Product

Resources

About