Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion

Kelly, Brandon M.; DiLello, Alexander; Graham, David

doi:10.3390/jlpea9030025

Cited by 8 publications

(11 citation statements)

References 27 publications

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“…Furthermore, optimizing the transistor sizing [20] improves the input-referred ofset and kick-back noise. As well, the complement diferential pair of the dynamic latch is employed to decrease the input-referred ofset voltage [7].…”

Section: Two-stage Dynamic Latchmentioning

confidence: 99%

“…Also, the two-stage dynamic latch comparator may be the familiar solution that trades of between power, speed, and noise [27]. Some researchers have used the tail transistor [2,4,7] or the PMOS latch comparator [2,4,12,102] to decrease the power consumption.…”

Section: Multistage Preamplifer Dynamic Latch Comparatormentioning

confidence: 99%

“…To improve the speed and power consumption of SAR ADC, an asynchronous scheme [7,11,16,17,24,35,44,53,58,64,86,91] is employed, as shown in Figure 35. Also, the complexity and area of SAR control logic are minimized.…”

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

“…Also, by using diferent switching strategies [27], the resolution, speed, and linearity can be enhanced to 14 dB, 17 MS/s, and 95 dB, respectively. An asynchronous converter of [7] is able to reduce power consumption by 14.7 nW.…”

Section: Fom W � P Adcmentioning

confidence: 99%

“…ADC for wireless biomedical applications [2] must have low power consumption for a long battery lifetime. Also, the applications of biomedical impose extra requirements on ADC to have a smaller chip area, medium resolution, and sampling speed ranging from a few KS/s to a few MS/s [7,8].…”

Section: Introductionmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Two-stage Dynamic Latchmentioning

confidence: 99%

Section: Multistage Preamplifer Dynamic Latch Comparatormentioning

confidence: 99%

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

Section: Fom W � P Adcmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Tyagi,

Mittal,

Kumar

2023

Phys. Scr.

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The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

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