Reconfigurable architecture design of FIR and IIR in FPGA

Paul, Arnob; Khan, Tanvir Zaman; Podder, Prajoy; Hasan, Md. Mehedi; Ahmed, Tanveer

doi:10.1109/spin.2015.7095408

Cited by 13 publications

(5 citation statements)

References 12 publications

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“…Therefore, this combination process reduces the sample period by [22] The pipelining and parallel processing combine techniques are used for lower power consumption. The pipeline technique decreases the capacitance which is charged or discharged in one clock cycle whereas parallel technique is increased the clock cycle for (10) charging or discharging the capacitance. The reduction of power consumption is due to the clock lines as compare with a pipeline system which needs to be operated using a high speed clock for same throughput or sample speed.…”

Section: Proposed Fir-based Iir Filtermentioning

confidence: 99%

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High performance IIR filter implementation on FPGA

Datta

Dutta

2021

Journal of Electrical Systems and Inf Technol

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This paper presents an improved design of reconfigurable infinite impulse response (IIR) filter that can be widely used in real-time applications. The proposed IIR design is realized by parallel–pipeline-based finite impulse response (FIR) filter. The FIR filters have excellent characteristics such as high stability, linear phase response and fewer finite precision errors. Hence, FIR-based IIR design is more attractive and selective in signal processing. In addition, the other two modern techniques such as look-ahead and two-level pipeline IIR filter designs are also discussed. All the said designs have been described in hardware description language and tested on Xilinx Virtex-5 field programmable gate array board. The implementation results show that the proposed FIR-based IIR design yields better performance in terms of hardware utilization, higher operating speed and lower power consumption compared to conventional IIR filter.

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Section: Proposed Fir-based Iir Filtermentioning

confidence: 99%

“…Again, S. Islam et al [9] proposed gate level IIR architecture is implemented on FPGA board and analysed its performance using impulse response. Similarly, A. Paul et al [10] developed the digital FIR filters in direct form and transposed form. The said filters are implemented on FPGA board and discussed the synthesis parameters.…”

mentioning

confidence: 99%

High performance IIR filter implementation on FPGA

Datta

Dutta

2021

Journal of Electrical Systems and Inf Technol

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“…It is constructed from the direct form by following the steps given below. 7,8 • Exchanging the input and output.…”

Section: Fir Filter W I T H Windowing Techniquementioning

confidence: 99%

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

Hussain

Parvin²

2020

SMSJ

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This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

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“…Digital signal processing filters can be implemented using both the infinite impulse response (IIR) or finite impulse response (FIR) approaches [3]. IIR approach is more preferred in practice since it requires less memory, it is easier to implement, and it is faster when compared to the FIR configuration for the same type of filter [4][5][6][7]. IIR filters are often used where a linear phase is not required.…”

Section: Introductionmentioning

confidence: 99%

FPGA Design of a Fourth Order Elliptic IIR Band-Pass Filter Using LabVIEW

Tatar¹,

Cicek²,

Bayar³

2021

European Journal of Science and Technology

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Infinite impulse response filters are often used to meet the demand of modern electrical engineering applications such as image processing, digital signal processing and telecommunications because of the high selectivity and computational efficiency. In missioncritical real-time applications, computational latency is usually intolerable. High-speed processing of data and the coefficients require a digital signal processor or an FPGA instead of a general-purpose microprocessor. In the last two decades, FPGAs have been applied to many fields of signal processing due to parallelism determined scalable performance and run-time reconfigurability. This study presents a LabVIEW driven FPGA hardware design of a fourth-order discrete-time IIR elliptic band-pass filter. The designed filter has 2 kHz low and 2.5 kHz high cut-off frequencies with 1dB pass-band ripple and 80dB stop-band attenuation. The expected behavior of the designed filter has been confirmed by the functional simulation of the developed VHDL model. LabVIEW FPGA resource estimation reports a compact footprint for the proposed design.

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Reconfigurable architecture design of FIR and IIR in FPGA

Cited by 13 publications

References 12 publications

High performance IIR filter implementation on FPGA

High performance IIR filter implementation on FPGA

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

FPGA Design of a Fourth Order Elliptic IIR Band-Pass Filter Using LabVIEW

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