Reconfigurable architecture of VDF filter for multidimensional data

Atitallah, Ahmed Ben; Boudabous, Anis; Khriji, Lazhar; Nouri, Mohammad

doi:10.1002/cta.1815

Cited by 10 publications

(11 citation statements)

References 13 publications

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“…In fact, in Ref. [22], a SW/HW design is proposed for the VDF filter and so it was successfully implemented. In addition, in Ref.…”

Section: Performance Evaluationmentioning

confidence: 99%

A New Adaptive Filter to Remove Impulsive Noise in Color Images

Atitallah

2022

IEEJ Transactions Elec Engng

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In this paper, a new adaptive vector directional distance filter (AVDDF) is proposed. The AVDDF filter is developed to remove the 'salt and papper' impulsive noise in color images. This algorithm consists in first step to detect pixels that are likely to have been contaminated with noise by using a threshold value. In second step, after recognizing the corrupted pixels, the smallest angular-magnitude distance is used to replace the noisy pixels. The proposed filter is tested with several standard color images which are contaminated with various levels of 'salt and pepper' impulsive noise (3%, 5%, 10%, 20% and 30%). The performance of the proposed filter is measured with peak signal-to-noise ratio (PSNR) and normalized color difference (NCD). The simulation results show that the proposed filter permits to ameliorate the performance of the classic vector directional distance filter (VDDF). Indeed, it provides an improvement by an average of 5% and 26% in the PSNR and NCD relative to the VDDF filter, respectively, with a small increase in the execution time by 6%. Besides, the AVDDF filter allows also an enhancement by an average of 2% and 14% in the PSNR and NCD relative to adaptive vector median filter (AVMF), respectively.

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“…In fact, in Ref. [22], a SW/HW design is proposed for the VDF filter and so it was successfully implemented. In addition, in Ref.…”

Section: Performance Evaluationmentioning

confidence: 99%

A New Adaptive Filter to Remove Impulsive Noise in Color Images

Atitallah

2022

IEEJ Transactions Elec Engng

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“…The experimental results show that this design can process 94 frames per second at 145 MHz. But, in [7], a hardware architecture for the VDF filter is proposed. This architecture is connected to the NIOS II processor and evaluated in hardware/software (HW/SW) codesign context.…”

Section: Introductionmentioning

confidence: 99%

An FPGA Design for Real-Time Image Denoising

Atitallah¹

2022

Computer Systems Science and Engineering

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The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).

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“…The traditional approach used to design and implement any algorithm in FPGA is Low-Level Synthesis (LLS) using hardware description language (HDL) such as VHSIC hardware description language (VHDL or Verilog). With such low-level design, it is possible to adjust the Register Transfer Level (RTL) description to generate an optimized hardware architecture [17][18][19]. But, this kind of design requires a lot of time and effort specially for complex algorithm.…”

Section: Introductionmentioning

confidence: 99%

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

Alanazi¹,

Atitallah²

2022

Computers, Materials &Amp; Continua

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As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for all Transform Unit (TU) block size, including 4 × 4, 8 × 8, 16 × 16 and 32 × 32. This architecture is designed using the High-Level Synthesis (HLS) and the Low-Level Synthesis (LLS) methods in order to compare and determine the best method to implement in real-time the DE/IT module. In fact, the C/C++ programming language is used to generate an optimized hardware design for DE/IT module through the Xilinx Vivado HLS tool. On the other hand, the LLS hardware architecture is designed by the VHSIC Hardware Description language (VHDL) and using the pipeline technique to decrease the processing time. The experimental results on the Xilinx XC7Z020 FPGA show that the LLS design increases the throughput in term of frame rate by 80% relative to HLS design with a 4.4% increase in the number of Look-Up Tables (LUTs). Compared with existing related works in literature, the proposed architectures demonstrate significant advantages in hardware cost and performance improvement.

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Reconfigurable architecture of VDF filter for multidimensional data

Cited by 10 publications

References 13 publications

A New Adaptive Filter to Remove Impulsive Noise in Color Images

A New Adaptive Filter to Remove Impulsive Noise in Color Images

An FPGA Design for Real-Time Image Denoising

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

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