Reconfigurable Computing Architectures

Tessier, Russell; Pocek, Kenneth L.; DeHon, André

doi:10.1109/jproc.2014.2386883

Cited by 170 publications

(72 citation statements)

References 263 publications

(246 reference statements)

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“…Reconfigurable computing consists of a device, such as an FPGA, performing computations with spatially programmable architectures [191,192]. It is rapidly establishing itself as a major discipline that inherits a wide body-of-knowledge from many disciplines including custom hardware design, digital signal processing, general purpose computing on sequential and multiple processors, and computer aided design.…”

Section: E Reconfigurable Dsp Implementation On Fpgamentioning

confidence: 99%

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Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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Section: E Reconfigurable Dsp Implementation On Fpgamentioning

confidence: 99%

“…FPGAs are specially useful for dynamic reconfiguration [192]. It allows for hardware configuration changes during different phases of the computation.…”

Section: E Reconfigurable Dsp Implementation On Fpgamentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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“…In order to support this kind of acceleration, and in the context of reconfigurable computing, it is mandatory to implement efficient architectures. Moreover, languages and computing models have to be developed on top of these architectures to achieve the expected results [4].…”

Section: Related Workmentioning

confidence: 99%

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Rodríguez

Valverde

Torre

2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Abstract-ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support.In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a memory model based on shared memory between host and compute device, which removes the overhead imposed by data transferences at global memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global memory through optimized DMA links. These local memories provide unified access, i.e. a continuous memory map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.

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“…While this reconfigurable computing approach has been discussed before [3], [4], the more capable multicore processors in these newer devices provides the ability to move the focus of reconfigurable computing systems away from static (or quasistatic) accelerators to a more software oriented view, where reconfiguration is a key enabler for reusing available hardware resources among multiple tasks. However, while the rapidly increasing logic density and more capable hard resources found in modern PSoC platforms, should make them applicable to a wider range of domains, such platforms have not seen significant use beyond specialist application domains, such as digital signal processing and communications.…”

Section: Introductionmentioning

confidence: 99%