Reconfigurable computing

Compton, Katherine; Hauck, Scott

doi:10.1145/508352.508353

Cited by 995 publications

(375 citation statements)

References 130 publications

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“…The first one consists in building Application Specific Integrated Circuits (ASICs) [3]. They are designed and built specifically to perform a given task, and thus they are very fast and efficient.…”

Section: Platforms For Algorithms Implementationmentioning

confidence: 99%

“…FPGAs are formed by logic blocks wired by reprogrammable connections, who can be configured to perform complex combinational functions (even to implement a GPP). FPGAs are used in many areas obtaining significant speed ups, such as automatic target recognition, string pattern matching, transitive closure of dynamic graphs, Boolean satisfiability, data compression and genetic algorithms [3], among others.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On the Design of a Hardware-Software Architecture for Acceleration of SVM’s Training Phase

Bustio-Martínez

Cumplido

Hernández-Palancar

et al. 2010

Advances in Pattern Recognition

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Abstract. Support Vector Machines (SVM) is a new family of MachineLearning techniques that have been used in many areas showing remarkable results. Since training SVM scales quadratically (or worse) according of data size, it is worth to explore novel implementation approaches to speed up the execution of this type of algorithms. In this paper, a hardware-software architecture to accelerate the SVM training phase is proposed. The algorithm selected to implement the architecture is the Sequential Minimal Optimization (SMO) algorithm, which was partitioned so a General Purpose Processor (GPP) executes operations and control flow while the coprocessor executes tasks than can be performed in parallel. Experiments demonstrate that the proposed architecture can speed up SVM training phase 178.7 times compared against a software-only implementation of this algorithm.

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Section: Platforms For Algorithms Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the Design of a Hardware-Software Architecture for Acceleration of SVM’s Training Phase

Bustio-Martínez

Cumplido

Hernández-Palancar

et al. 2010

Advances in Pattern Recognition

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“…Once deployed in field, these devices always run the same application, in a well-characterized context. It is therefore possible to spend a large amount of time for finding an optimal allocation and scheduling offline and then deploy it on the field, instead of using on-line, dynamic (sub-optimal) schedulers [17,18]. The multi-processor system we consider consists of a pre-defined number of distributed Processing Elements (PE) as depicted in Figure 1.…”

Section: The Architecturementioning

confidence: 99%

Stochastic Allocation and Scheduling for Conditional Task Graphs in MPSoCs

Lombardi

Milano

2006

Principles and Practice of Constraint Programming - CP 2006

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Abstract. This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph characterizing a target application and a target architecture with alternative memory and computation resources, we compute an allocation and schedule minimizing the expected value of communication cost, being the communication resources one of the major bottlenecks in modern MPSoCs. Our approach is based on the Logic Based Benders decomposition where the stochastic allocation is solved through an Integer Programming solver, while the scheduling problem with conditional activities is faced with Constraint Programming. The two solvers interact through no-goods. The original contributions of the approach appear both in the allocation and in the scheduling part. For the first, we propose an exact analytic formulation of the stochastic objective function based on the task graph analysis, while for the scheduling part we extend the timetable constraint for conditional activities. Experimental results show the effectiveness of the approach.

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“…Meanwhile, RAs also maintain post-fabrication flexibility because they can reconfigure themselves for standard updates or new application requirements. Currently, field programmable gate arrays (FPGAs) still dominate the reconfigurable computing field [6]. However, the bit-level, fine-grained granularity of FPGAs has significant costs in terms of routing area, speed and configuration time.…”

Section: Introductionmentioning

confidence: 99%

“…To achieve these performance benefits and support a wide range of applications, reconfigurable systems are usually formed with a combination of CGRAs and a general purpose microprocessor [6]. The processor performs operations that cannot be efficiently performed in reconfigurable logic, such as data-dependent controls.…”

Section: Introductionmentioning

confidence: 99%

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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Reconfigurable computing

Cited by 995 publications

References 130 publications

On the Design of a Hardware-Software Architecture for Acceleration of SVM’s Training Phase

On the Design of a Hardware-Software Architecture for Acceleration of SVM’s Training Phase

Stochastic Allocation and Scheduling for Conditional Task Graphs in MPSoCs

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

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