Reconfigurable hardware: The holy grail of matching performance with programming productivity

Abstract

International audienceMany reconfigurable hardware architectures have been proposed so far, ranging from FPGAs to coarse grained architectures. Reconfigurability can be intended in several ways, and a number of diverse solutions have been proposed. One of the most relevant issues that have emerged is that the performance gain offered by reconfigurable hardware is balanced by relevant difficulties in their programming, which often inhibit its utilization in many appealing fields and ultimately jeopardize its diffusion. The solution for enabling higher productivity in application mapping likely do not reside only in the development of better tools, but also of more usable designs. This paper gives an overview of different reconfigurable architectures and related design flows proposed over the last years, including commercial offers and efforts coming from academia, analyzes the challenges they pose to the application developer and focuses on the latest alternatives to mitigate the design productivity issue

The Paramountcy of Reconfigurable Computing

“…Because of the inevitable manycore architecture contemporary computer systems are in an alldominant programmability crisis. The progress of performance is massively stalled because of this "programming wall" caused by lacking scalability of parallelism and an ubiquitous programmer productivity gap 146,147,150 . Later in this chapter we show that reconfigurability is the silver bullet to obtain massively bet-ter energy efficiency as well as much better performance by the upcoming heterogeneous methodology of HPRC (high performance reconfigurable computing).…”

“…Some tools at least halfways protect the developer from hardware design issues or even explicit parallel programming, making the sorting out of CPU and FPGA code mappings the responsibility of the compiler and runtime system. We should characterize this niche and the progress of High-Performance Reconfigurable Computing, as well as the associated challenges, and, we should characterize the systemic productivity problem 146,242 We have to devise an orchestrated multilevel research agenda that is needed to move forward and identify the potential practical next steps for the community 264 .…”

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

“…An important issue that has emerged in context of reconfigurable architectures is that the performance gain they offer is balanced out by the difficulties in their programming [10]. Realizing this, considerable effort was devoted in refining a programming model of the DRMP that is simple to understand and use, and will enable meeting the strict time-to-market constraints that wireless system designers face.…”

“…Coarse-grained architectures can lead to relatively efficient implementations if the intended functionality matches well with the architecture of the functional units. They minimize the overheads that are caused by routing and configuration channels that affect more fine-grained architectures like FPGAs [10].…”

“…It provides the performance benefits of hardware while still being flexible like software by being reconfigurable post-fabrication. The synergy between dynamic programmability and computational power makes reconfigurable hardware a very attractive option to deploy computation-intensive tasks in application fields that are constantly changing [10]. Fig 2.2 which has been adapted from [18] compares these three different design paradigms.…”