Reconfigurable Nanowire Transistors with Multiple Independent Gates for Efficient and Programmable Combinational Circuits

Trommer, Jens; Heinzig, André; Baldauf, Tim; Mikolajick, Thomas; Weber, Walter M.; Raitza, Michael; Völp, Marcus

doi:10.3850/9783981537079_0206

Cited by 47 publications

(38 citation statements)

References 11 publications

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“…The most straightforward way of doing this is by lowering the Schottky barrier height of the source and drain contacts, either through work function engineering of the silicide or through doping at the contact region. For instance, Zhang et al and recently Mauersberger et al have shown that a segregation of dopants near the Schottky barrier interface can be used to reduce the barrier and increase the output current [21], [22]. This is exemplarily shown for the device used in this study in Fig.…”

Section: A Device Level Performance Enhancementsmentioning

confidence: 52%

“…However, in order to deal with the charge sharing problem, we will exploit a completely different feature of those devices. It has been shown, both by simulations [21] and measurements [11], [12] that MIGFETs support an internal wired-AND functionality, i.e. a single transistor can be described as an equivalent circuit of several MOSFETs in series.…”

Section: Schottky Barrier Based Transistors With Multiple Indepementioning

confidence: 99%

“…More details about the simulation setup and considered transport models can be found in Ref. [16], [21]. The data is compared to mixed-mode simulations of a CMOS reference design in 22 nm FD-SOI technology [23].…”

Section: Eliminating Charge Sharing At the Device Levelmentioning

confidence: 99%

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Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Trommer

Simon

Slesazeck

et al. 2020

IEEE J. Electron Devices Soc.

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Charge sharing poses a fundamental problem in the design of dynamic logic gates, which is nearly as old as digital circuit design itself. Although, many solutions are known, up to now most of them add additional complexity to a given circuit and require careful optimization of device sizes. Here we propose a simple CMOS-technology compatible transistor level solution to the charge sharing problem, employing a new class of field effect transistors with multiple independent gates (MIGFETs). Based on mixed-mode simulations in a coordinated device-circuit co-design framework, we show that their underlying device physics provides an inherent suppression of the charge sharing effect. Circuit layouts and design examples are discussed, which elucidate the fundamental differences in circuit topology to classical CMOS designs. For example it is shown that dynamic gates from MIGFET scale much better with stack height of long serial networks, leading to an increased circuit performance, while also providing higher signal stability.

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Section: A Device Level Performance Enhancementsmentioning

confidence: 52%

Section: Schottky Barrier Based Transistors With Multiple Indepementioning

confidence: 99%

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Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Trommer

Simon

Slesazeck

et al. 2020

IEEE J. Electron Devices Soc.

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“…Multiple gates are also extremely useful to manipulate the potential landscape within devices to realize and study for example reconfigurable transistors for programmable combinational circuits . Moreover, if the gate electrodes are sufficiently small, they enable tuning the potential landscape within a device on the nanoscale to realize for example resonant tunneling diodes, coupled quantum dot devices etc.…”

Section: Electrostatic Doping Of Field‐effect Transistorsmentioning

confidence: 99%

Alternatives for Doping in Nanoscale Field‐Effect Transistors

Riederer

Grap

Fischer

et al. 2018

Physica Status Solidi (a)

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In the present article, alternatives to impurity doping in nanoscale field‐effect transistors (FETs) are investigated. The discussion is based on conventional and tunnel FETs. The impact of dopant deactivation due to dielectric mismatch or quantization, random dopant effects, and the degeneracy level on the performance is discussed. As alternatives metal‐semiconductor‐contacts, gate‐controlled doping and an interface engineering approach are studied. One of the main requirements for proper device functionality is the existence of a band gap in the contacts. Thus, metal‐semiconductor contacts are less suited since they lead to ambipolar operation with increased leakage and to a deteriorated on‐state performance. With gate‐controlled doping, electrodes areused to create doped regions leaving behind a pristine band gap. Moreover, it enables reconfigurable devices with nFET, pFET and tunnel FET operation. Furthermore, with multiple nanoscale gates, electrostatic doping allows manipulating the potential within the device on the nanoscale. Experimental demonstrations of such devices with triple‐gates and multiple gate structures are presented. Finally, the interface engineering approach allows combining a metallic contact electrode with an almost unmodified band gap in the source/drain contacts by adjusting an ultrathin insulator in‐between metal and semiconductor yielding quasi‐doped contacts whose polarity depends on the work function of contact metal.

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“…D EVICE technologies with enhanced functionality or advantageous physical properties over established CMOS devices are in research with the goal to supplement or even replace current technologies. Such research includes reconfigurable transistors [1]- [5], graphene nano ribbonbased devices [6], [7] or mixed-dimensional heterostructurebased devices [8]. Alongside, alternative computation architectures move into focus, like asynchronous and approximate computing [9].…”

Section: Introductionmentioning

confidence: 99%

Quantitative Characterization of Reconfigurable Transistor Logic Gates

et al. 2020

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We present a new approach for early analysis of logic gates that is based on formal methods. As device technology research takes years and is very expensive, it is desirable to evaluate a technology's potential as early as possible, which is hard to do with current techniques. The actual impact of new devices on circuit design and their performance in complex circuits, are difficult to predict using simulationbased techniques. We propose a new approach that supplements simulation-based analysis and enables the development of standard cells alongside ongoing fundamental device research. Thereby, it potentially shortens the development cycle and time to market of a new technology. We develop a new discrete charge-transport model for electrical networks and a new flexible model of polarity-reconfigurable transistors as our formal basis. These models make circuit designs accessible to an analysis using probabilistic model checking and power our experiments. Besides worst-case analysis, we leverage measures hardly accessible to simulation such as average delay and average energy consumption per switching operation. We complement this with an automated design-space exploration that yields all reasonable implementations of a switching function built with reconfigurable transistors. After demonstrating the accuracy of our approach by comparison with finite element method analysis results, we undergo a comprehensive design-space exploration and analysis of the 3-minority function. The quantitative results are ranked with respect to various performance metrics, and we analyze the most promising circuit implementations in detail to derive a design guide that yields the best implementation for given statistics of the input patterns.

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Reconfigurable Nanowire Transistors with Multiple Independent Gates for Efficient and Programmable Combinational Circuits

Cited by 47 publications

References 11 publications

Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Alternatives for Doping in Nanoscale Field‐Effect Transistors

Quantitative Characterization of Reconfigurable Transistor Logic Gates

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