Reconfigurable Readback-Signal Generator Based on a Field-Programmable Gate Array

Chen, Jinghuan; Moon, Jaekyun; Bazargan, Kia

doi:10.1109/tmag.2004.826913

Cited by 17 publications

(7 citation statements)

References 18 publications

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“…Chen et al [10] propose a hardware implementation based on the use of a lookup table to store the ICDF. This approach requires a large memory to generate Gaussian samples with a large magnitude.…”

Section: Icdfmentioning

confidence: 99%

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

Gutierrez

Torres

Valls

2012

IEEE Trans. Circuits Syst. II

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Abstract-We propose a generalization of the matched subspace filters for the detection of unknown signals in a background of non-Gaussian and non-independent noise. The generalization is based on a modification of the Rao test by including a linear transformation derived from Independent Component Analysis (ICA). Receiver Operating Characteristic (ROC) curves computed for simulated examples illustrate the significant improvement achieved with the generalized solution.Index Terms-Rao test, matched subspace filter, non-Gaussian noise, ICA.

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Section: Icdfmentioning

confidence: 99%

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

Gutierrez

Torres

Valls

2012

IEEE Trans. Circuits Syst. II

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“…Other sample applications are active filters [44], ac drives [45], image processing [46], signal/function generators [47], signal transforms [48], or artificial vision [49]. A subject of increasing interest is the digital generation of control signals for electronics switches in power converters [50], [51].…”

Section: E Digital Signal Processingmentioning

confidence: 99%

Features, Design Tools, and Application Domains of FPGAs

Rodríguez-Andina

Moure

Valdés

2007

IEEE Trans. Ind. Electron.

342

111

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In the past two decades, advances in programmable device technologies, in both the hardware and software arenas, have been extraordinary. The original application of rapid prototyping has been complemented with a large number of new applications that take advantage of the excellent characteristics of the latest devices. High speed, very large number of components, large number of supported protocols, and the addition of readyto-use intellectual property cores make programmable devices the preferred choice of implementation and even deployment in mass production quantities. This paper surveys the advanced features, design tools, and application domains for field-programmable gate arrays (FPGAs). The main characteristics and structure of modern FPGAs are first described to show their versatility and abundance of available design resources. Software resources are also discussed, as they are the main enablers for the efficient exploitation of the design capabilities of these devices. Current application domains are described, such as configurable computing, dynamically reconfigurable systems, rapid system prototyping, communication processors and interfaces, and signal processing. This paper also presents the authors' prospective view of how FPGAs will evolve to enter new application domains in the future.

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“…To generate GVs, it transforms uniform random variables into Gaussian variates by approximating the nondecreasing inverse of the Gaussian cumulative distribution function (CDF) as . Since there is no closed-form approximation for , the GVG in [35] uses a lookup table to store the CDF inverse. This method requires a large memory to generate accurate GVGs at the tails of the Gaussian distribution.…”

Section: Gvg Algorithms and Related Workmentioning

confidence: 99%

A Compact and Accurate Gaussian Variate Generator

Alimohammad

Fard

Cockburn

et al. 2008

IEEE Trans. VLSI Syst.

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Abstract-A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e., with a proposed 16-bit datapath up to 15 times the standard deviation ) with only small variations in hardware utilization, and without degrading the output sample rate. Polynomial curve fitting is utilized along with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typical instantiation of the proposed GVG occupies only 534 configurable slices, two on-chip block memories, and three dedicated multipliers of the Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian variates (GVs) per second within a range of 6 66 . To accurately achieve a range of 9 4 , the GVG uses 852 configurable slices, three block memories, and three on-chip dedicated multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and performance of a GVG implemented in a 90-nm CMOS technology are also given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness-of-fit tests.Index Terms-Box-Muller (BM) algorithm, field-programmable gate array (FPGA), Gaussian noise generator (GNG), low bit-error rate simulation, random number generation.

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Reconfigurable Readback-Signal Generator Based on a Field-Programmable Gate Array

Cited by 17 publications

References 18 publications

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

Features, Design Tools, and Application Domains of FPGAs

A Compact and Accurate Gaussian Variate Generator

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