Reconfiguration Control Networks for TMR Systems with Module-Based Recovery

2016 International Conference on Field-Programmable Technology (FPT)

et al. 2016

Self Cite

Space processing applications deployed on SRAMbased Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). Compared with the well-known SEU mitigation solution-Triple Modular Redundancy (TMR) with configuration memory scrubbing-TMR with module-based error recovery (MER) is notably more energy efficient and responsive in repairing soft-errors in the system. Unfortunately, TMR-MER systems also need to resort to scrubbing when errors occur in sub-components, such as nets, which are not recovered by MER. This paper addresses this problem by proposing a fine-grained module-based error recovery technique that without additional system hardware can localize and correct errors that classic MER fails to do. We evaluate our proposal via a fault-injection campaign on a Xilinx Artix-7 application circuit and compare the reliability, the error correction latency and the energy cost of repairing errors, of our proposal with those of a conventional MER approach and with periodic and on-demand blind scrubbing. We find the reliability of our proposal to be the highest and the energy expenditure to be the lowest amongst those methods considered.

Section: Configuration Memory Error Detection Classification Anmentioning

confidence: 99%

Section: Repair Strategymentioning

confidence: 99%

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Fine-grained module-based error recovery in FPGA-based TMR systems

Zhao

Agiakatsikas

2016 International Conference on Field-Programmable Technology (FPT)

et al. 2016

Self Cite

“…Hence, reading and writing the configuration memory are fundamental operations for detecting and recovering from configuration errors. For example, in MER, the existence of an error can be identified by reading voter status via the configuration port [12], [13]. After an error is detected, MER approaches typically recover the error by partially reconfiguring the erroneous module [14], [15].…”

Section: Related Workmentioning

confidence: 99%

“…Cast Study 1 demonstrates the use of PCC to check voter status via the ICAP used in Modular Error Recovery (MER) [13] (See Figure 4). The system consists of a number of synthetic compute nodes with each node containing one voter and three identical copies of synthetic computational modules.…”

Section: A Case 1: Icap-based Voter Checkingmentioning

confidence: 99%

A Programmable Configuration Controller for fault-tolerant applications

Gong

2016 International Conference on Field-Programmable Technology (FPT)

et al. 2016

Self Cite

Abstract-FPGAs are promising candidates for computational tasks in space applications. However, they are susceptible to radiation-induced errors, the most common failure being due to the corruption of their configuration memory. Module-based partial reconfiguration and frame-based scrubbing are the two most commonly used techniques for detecting and recovering from configuration memory errors. Both methods require userdesigned reconfiguration controllers (RC) to read and write FPGA configuration memory data. This paper proposes a Programmable Configuration Controller (PCC) specifically designed for fault-tolerant applications. PCC has a soft Application Specific Instruction Set Processor (ASIP) architecture. The PCC is software programmable using the C language, which allows it to be used in a wide variety of fault-tolerant applications with minimal design and/or hardware overhead. PCC also has instruction extensions to accelerate commonly-used reconfiguration operations such as reading and writing configuration data. Through 5 case studies, we demonstrate that the use of an ASIP architecture for reconfiguration control in applications prone to radiation-induced corruption strikes the right balance between speed, resource utilization and flexibility.

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

IET Computers & Digital Techniques

Cetin²,

Diessel³

2018

Self Cite

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR-MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15-23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin. Nomenclature Symbol Definition N number of TMR components in the system Ck component k, k = 1, …, N O kn Ck is observed for the nth time by checking its voter(s) Δt o time period between successive voter observations (assumed to be constant for a given system setting) Δt dk time period between two consecutive observations of Ck Δt rk time period to recover a faulty module of Ck Δt k total time period over which Ck can fail Δt di j time period between successive observations of Ci and Cj Δt d′i j average time period between two consecutive observations of Ci in the interval between two consecutive observations of Cj IET Comput. Digit. Tech.