Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture

Seto, Daisaku; Watanabe, Minoru

doi:10.1109/fpt.2007.4439262

Cited by 8 publications

(8 citation statements)

References 8 publications

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“…Therefore, a holographic configuration inevitably reduces the retention time of a gate array taking the DORGA architecture. The retention time of a single holographic configuration in the DORGA architecture has been measured [15]. Results verify that the influence of background light is slight under a single optical configuration.…”

Section: B Dorga Architecturementioning

confidence: 77%

Analysis of retention time under multi-configuration on a DORGA

Seto

Watanabe

2008

2008 IEEE International SOC Conference

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Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. Up to now, dynamic optically reconfigurable architecture has been proposed to increase the gate count of the ORGA-VLSI part, which uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memories. Consequently, extremely high gate count ORGAs have been realized. However, in this architecture, since background diffraction light of configuration contexts reduces the retention time of circuit information stored in junction capacitances of photodiodes, it has remained a concern that under multiconfiguration, an optical configuration can reduce the retention time of other circuits that have already been programmed before the configuration and are functioning on a gate array. This paper clarifies that the dynamic optically reconfigurable architecture is effective even under multi-configuration.

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Section: B Dorga Architecturementioning

confidence: 77%

Analysis of retention time under multi-configuration on a DORGA

Seto

Watanabe

2008

2008 IEEE International SOC Conference

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“…To date, estimation of the DORGA architecture using a liquid crystal holographic memory has been conducted; its availability has been demonstrated [12]. However, the resolution of the liquid crystal holographic memory is very low and the number of storable configuration contexts is limited to four.…”

Section: Figure 1 Optical Reconfiguration Circuits Of a Static Technmentioning

confidence: 99%

A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory

Seto

Watanabe

2008

2008 IEEE Computer Society Annual Symposium on VLSI

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To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. To date, estimation of the DORGA architecture using a liquid crystal holographic memory has been conducted, thereby demonstrating its availability. However, because the resolution of the liquid crystal holographic memory is very low and because the storable configuration contexts are numerically limited to four, that estimation cannot be considered a practical experiment. Therefore, this paper presents a practical demonstration of the DORGA architecture using a silver-halide holographic memory that can store over 3,000 configuration contexts. The DORGA architecture performance, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.

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“…The advantage of the context switch FPGA is a very short transition time from one configuration to another. Switch occurs within one or two clock cycles [97]. One more significant problem that arises from the implementation of additional configuration memory plane on an FPGA device is the increased power consumption [68,18].…”

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

“…Therefore, context switching is not cost-efficient in the solutions that are used for industrial applications and where cost is critical. The external configuration controller of the multi-context FPGA is not discussed in detail by [97,68,18]. However, it is assumed to be a conventional configuration controller used in most of the FPGA devices.…”

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

“…On the other hand, the internal configuration controller can be considered as an array of multiplexers that perform a selection of the configuration IP-core from the available SRAM cells. Configuration memory management also was not addressed in the [97,68,18] papers regarding the multi-context FPGAs, and therefore, cannot be evaluated in detail in this overview.…”

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

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The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

Kirischian¹

2021

Preprint

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The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

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Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture

Cited by 8 publications

References 8 publications

Analysis of retention time under multi-configuration on a DORGA

Analysis of retention time under multi-configuration on a DORGA

A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

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