To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, estimation ofa perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. This paper presents a perfect DORGA architecture including a holographic memory. The performances of the DORGA architecture, in particular the reconfiguration context retention time, were analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.
We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm(2) chip using an 0.35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 μs partial reconfiguration.
To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. To date, estimation of the DORGA architecture using a liquid crystal holographic memory has been conducted, thereby demonstrating its availability. However, because the resolution of the liquid crystal holographic memory is very low and because the storable configuration contexts are numerically limited to four, that estimation cannot be considered a practical experiment. Therefore, this paper presents a practical demonstration of the DORGA architecture using a silver-halide holographic memory that can store over 3,000 configuration contexts. The DORGA architecture performance, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.
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