Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays

Abstract

Abstract-Negative Bias Temperature Instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI since one of the PMOS devices in the memory cell always has an input of '0'. Previously proposed recovery techniques for SRAM cells aim to balance the degradation of the two PMOS devices by attempting to keep their inputs at a logic '0' exactly 50% of the time. However, one of the devices is always in the negative bias condition at any given time. In this paper, we propose a technique called Recovery Boosting that allows both PMOS devices in the memory cell to be put into the recovery mode by slightly modifying the design of conventional SRAM cells. We present the circuit-level design of an issue queue that uses such cells and perform SPICElevel simulations to verify its functionality and quantify area and power consumption. We then conduct an architecturelevel evaluation of the performance and reliability of using an area-neutral design of such an issue queue using the M5 simulator and the SPEC CPU2000 benchmark suite. We show that recovery boosting provides a 56% improvement in the static noise margin for the issue queue while having very little impact on power consumption and a negligible loss in performance.

A Review of NBTI Degradation and its Impact on the Performance of SRAM

“…A novel approach for recovery boosting is proposed in [24] in which slight modification in SRAM cell design is made to ensure that both PMOS transistors in the SRAM cell can be put into the recovery mode. Modified SRAM cell design for recovery boosting is shown in Fig.8 Both PMOS devices in SRAM are put to recovery mode by raising the ground potential to vdd by making CR signal "0" and both BL and BLB lines are precharged to vdd.…”

“…Research work carried out in [2,19,20,21,22] deals with NBTI degradation effects on SRAM and its important performance parameters. Design techniques employed to mitigate the NBTI degradation effects are discussed in [19,20,22,24,33].…”

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

“…Other research efforts have focused on balancing the amount of time that logic '0' and '1' values are stored in the cells with the aim to provide a BTI-optimal duty cycle distribution [18,19], and by implementing redundancy into the cache design to combat BTI-induced wearout [20]. Gunadi et al [19] also proposed to mitigate the HCI degradation by providing a uniform distribution of cache accesses across sets.…”

Enhancing the L1 Data Cache Design to Mitigate HCI

“…Shin et al [5] implement redundancy (additional cell regions) in the cache, which are used when the system identifies that the original regions are being affected by aging. Other work [6] modified the original SRAM cell design used to implement the issue queue. Finally, in [8], Tiwari and Torrellas dynamically adapt the effects of temperature and voltage on aging to enlarge the processor lifetime.…”