Reduce scrap: control oxide loss in SC1

Maines, H.; Rathmell, M.; Veldhuis, L.L.M.

doi:10.1109/asmc.2002.1001600

Cited by 2 publications

(1 citation statement)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Maines et al reported that the thinning of the screen oxide in SC1 7 could shift the depth of a shallow implant in addition to the amount of dopant that penetrates into the silicon, resulting in a measurable change in the threshold voltage. 8 The gate oxide quality was improved due to the reduced surface roughness with a low temperature SC1 cleaning prior to gate oxidation. [9][10][11] On the other hand, the silicon surface is oxidized by HO 2 Ϫ and the SiO 2 layer is then etched by OH Ϫ in SC1 cleaning or the silicon surface is directly etched by OH Ϫ .…”

mentioning

confidence: 99%

SC1 Cleaning Effect on Electrical Characteristics of 256 Mbit Mobile DRAM with Dual Gate Oxide

Lee

Hwang

et al. 2004

J. Electrochem. Soc.

View full text Add to dashboard Cite

The electrical effects of RCA standard clean 1 ͑SC1͒ prior to the second gate oxidation for dual gate oxide formation was investigated by splitting the SC1 cleaning time for a 256 Mbit mobile dynamic random access memory ͑DRAM͒ operating at 1.8 V. The etch rate with respect to the oxide by SC1 cleaning was approximately 1.6 Å/min. The threshold voltage (V tn) of the n-type metal-oxide-semiconductor field-effect transistor ͑nMOSFET͒ in the thin oxide region was shown to be a similar value with varying the SC1 time, while the absolute threshold voltage (͉V tp ͉) of the pMOSFET increased by 4%. In the thick oxide MOSFETs, V tn decreased by 15%, while on the contrary, ͉V tp ͉ increased by 7%. V tn was found to be mainly dependent on the decreased gate oxide thickness due to the deep boron peak depth. However, ͉V tp ͉ appeared to be more dependent on the decrease of surface boron concentration due to a shallow boron peak and also to the influence by the enhanced pocket implantation effect. Consequently, it is proposed that the SC1 cleaning time should be less than 300 s in order to retain the reliable electrical properties for both thin and thick gate oxide MOSFETs due to the drastic decrease of V tn and breakdown voltage (BV dssn).

show abstract

mentioning

confidence: 99%