With the advent of shallow source/drains in advanced CMOS, PMOS transistors can become susceptible to source to well leakage. Products which use shallow trench isolation (STI) are susceptible to thin trench oxide which can lead to leaky transistors as the cobalt silicide gets formed around the edges of the active region, creating a current path when trench oxide is thin. PMOS transistors are more susceptible to this leakage current mechanism as the PMOS source / drain implants are shallower than the NMOS.Implementation of feed forward of post CMP trench oxide thickness to trench recess etch time can compensate for incoming variation from STI CMP. This results in a more consistent field oxide thickness, and a more consistent field oxide to active area step height. This is accomplished by adjusting the trench recess HF time based on the incoming oxide thickness. P+ contact leakage on test lots decreased significantly as a result of the STI trench recess feed forward process as seen on Figure 3 between the TEST and CONTROL legs of the experiment.

In this study, we characterize thermal silicon dioxide, plasma enhanced CVD tetraorthosilicate oxide (PECVI) TEOS) and phosphorous doped silicate glass (PSG) etch rates in SC1 as a function of termperature and concentration. We also measure the effect of implant screen oxide loss in SC1 on transistor voltage turn on and elucidate ways to reduce scrap due to oxide loss in SC1.

Cobalt silicide is used to reduce contact resistance for sub-micron technology such as 0.25um CMOS. At National Semiconductor, a thin oxide is used to protect areas that are not to be silicided. The selective removal of this oxide to form the silicide mask is critical as it occurs in the highly sensitive cobalt silicide module where neither over nor under etch is acceptable. The final etch uses a low power, CHF 3 /Ar recipe with good across wafer uniformity. In keeping with the advanced process control methodology at National, the etch is end pointed to reduce wafer-to-wafer and etch chamber variability. This paper contains integration aspects of the cobalt silicide module as well as the specifics of the new etch process. The effects of power, pressure and gas flows and details of the end point set up are reviewed, as well as cross section analysis and electrical responses.