With the advent of shallow source/drains in advanced CMOS, PMOS transistors can become susceptible to source to well leakage. Products which use shallow trench isolation (STI) are susceptible to thin trench oxide which can lead to leaky transistors as the cobalt silicide gets formed around the edges of the active region, creating a current path when trench oxide is thin. PMOS transistors are more susceptible to this leakage current mechanism as the PMOS source / drain implants are shallower than the NMOS.Implementation of feed forward of post CMP trench oxide thickness to trench recess etch time can compensate for incoming variation from STI CMP. This results in a more consistent field oxide thickness, and a more consistent field oxide to active area step height. This is accomplished by adjusting the trench recess HF time based on the incoming oxide thickness. P+ contact leakage on test lots decreased significantly as a result of the STI trench recess feed forward process as seen on Figure 3 between the TEST and CONTROL legs of the experiment.