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A tungsten etchback process has been developed using a bipolar electrostatic clamp (ESC) in a parallel-plate, single wafer etcher with a 13.56 MHz power applied to the top electrode. The transfer of a SF6/N2 etchback process from a mechanically clamped to a bipolar electrostatically clamped system was not straightforward. Initially, the ESC system produced more tungsten residue and a lower etch rate than a mechanically clamped system. By optimizing the rf grounding circuit of the ESC, the residue was reduced. A Langmuir probe study demonstrated that the ion current profile varied strongly with electrode spacing for SF6 but not for gases such as Cl2 or Ar. Both the tungsten residue and the anomaly in the ion current profile were eliminated by the proper choice of electrode spacing. Energetic electrons have been proposed as the cause of the unusual ion current profile. Process results have been optimized with the new electrode spacing, allowing the fabrication of submicrometer tungsten plugs on 200 mm wafers. The tungsten plug recess, which is controllable by wafer temperature and process conditions, is typically 0.1 μm.

Cobalt silicide is used to reduce contact resistance for sub-micron technology such as 0.25um CMOS. At National Semiconductor, a thin oxide is used to protect areas that are not to be silicided. The selective removal of this oxide to form the silicide mask is critical as it occurs in the highly sensitive cobalt silicide module where neither over nor under etch is acceptable. The final etch uses a low power, CHF 3 /Ar recipe with good across wafer uniformity. In keeping with the advanced process control methodology at National, the etch is end pointed to reduce wafer-to-wafer and etch chamber variability. This paper contains integration aspects of the cobalt silicide module as well as the specifics of the new etch process. The effects of power, pressure and gas flows and details of the end point set up are reviewed, as well as cross section analysis and electrical responses.

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Plasma etch has always played an important role in microelectronic manufacturing. Defects observed at post-etch usually have significant impact on yield. The visual post-etch defects are generally divided into three major categories. Those defects discovered at etch but not generated by etch, the defects generated during etch, and the defects generated by interaction between different process layers. The prior layer defects are the defects uncovered by the etch process but originated in prior layers such as film or lithography. The true plasma etch-generated defects usually consist of processinduced defects and equipment defects. Process integration defects are those type of defects that are caused by interaction between different layer stoichiometry and process chemistry. The origin of these defects observed at post-etch need to be identified and isolated in order to make defect reduction in the plasma etch area manageable.The best defect yield management strategy is to use an integrated monitoring scheme consisting of in-line, short-loop, and equipment monitor wafers to monitor defect levels in the production line and to troubleshoot yield loss caused by defects. This paper discusses how to set up effective integrated short-loop patterned etch and blank resist-coated etch equipment monitors to isolate the contribution of different components of post-etch defects listed above.