Reduced Complexity Architecture for Convolution Based Discrete Cosine Transform

Mamatha, I.; Raj, Jina; Tripathi, Shikha; Sudarshan, T. S. B.

doi:10.1109/ised.2013.20

Cited by 2 publications

(3 citation statements)

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“…The architecture with systolic array and post processing unit is shown in Fig.3. Mamatha et.al [15] proposed a reduced complexity architecture for convolution based 1D DCT which uses a pair of systolic arrays instead of 2 pairs as proposed in Meher [13]. These two systolic arrays have similar tag bits as that of the first and seventh systolic array of 1D DFT structure.…”

Section: Post Processing Satge( Stage 3)mentioning

confidence: 99%

“…Hence, these two systolic arrays can be utilized for 1D DFT as well as 1D DCT computations. We refer to [15] for the complete architecture for 1D DCT comprising preprocessing, systolic array and post processing stage. Using the two structures a unified architecture for 1D DCT and 1D DFT can be obtained where preprocessing and post processing stages are unique for 1D DCT and 1D DFT.…”

Section: Post Processing Satge( Stage 3)mentioning

confidence: 99%

“…The proposed architecture is simulated and synthesized for validation. The work proposed by Mamatha et.al [15] for N point 1D-DCT using convolution formulation where DCT is divided into two pairs of [(M-1)/2]-point cyclic convolution with M as an odd number and M=N/2 is observed to have similar structure. Using the two architectures, a unified architecture for 1D-DFT and 1D-DCT is also proposed in this work.…”

Section: Introductionmentioning

confidence: 99%

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Systolic architecture implementation of 1D DFT and 1D DCT

Mamatha

Raj

Tripathi

et al. 2015

2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES)

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Discrete Fourier Transform is widely used in signal processing for spectral analysis, filtering, image enhancement , OFDM etc.. Cyclic convolution based approach is one of the techniques used for computing DFT. Using this approach an N point DFT can be computed using four pairs of [(M-1)/2]-point cyclic convolution where M is an odd number and N=4M. This work proposes an architecture for convolution based DFT and its FPGA implementation. Proposed architecture comprises of a pre-processing element, systolic array and a post processing stage. Processing element of systolic array uses a tag bit to decide on the type of operation (addition/subtraction) on the input signals. Proposed architecture is simulated for 28 point DFT using ModelSim 6.5 and synthesized using Xilinx ISE10.1 using Vertex 5 xc5vfx100t-3ff1738 FPGA as the target device and can operate at a maximum frequency of 224.9MHz. The performance analysis is carried out in terms of hardware utilization and computation time and compared with existing similar architectures. Further, as the convolution based DCT has two systolic arrays similar to that of DFT , a unified architecture is proposed for 1D DFT/1D DCT.

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Section: Post Processing Satge( Stage 3)mentioning

confidence: 99%

Section: Post Processing Satge( Stage 3)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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