Reduced Complexity Path Selection Networks for M-Algorithm Read Channel Detectors

Power, M.; Tosi, Sébastien

doi:10.1109/tcsi.2008.920110

Cited by 2 publications

(1 citation statement)

References 23 publications

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“…The M-algorithm implementation in [22] leverages a degree of partial sorting among the generated B · 2 k nodes at the expansion stage. Although our implementation does not use their technique, their work is, to the best of our knowledge, the first to recognize that a full sort is not necessary to achieve good performance in the M-algorithm.…”

Section: Existing M-algorithm Implementationsmentioning

confidence: 99%

A hardware spinal decoder

Iannucci

Fleming

Perry

et al. 2012

Proceedings of the Eighth ACM/IEEE Symposium on Architectures for Networking and Communications Systems

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Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel "α-β " incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters.We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.

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Section: Existing M-algorithm Implementationsmentioning

confidence: 99%