Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs

Mizutani, Tomoko; Yamamoto, Y.; Makiyama, Hideki; Tsunomura, T.; Iwamatsu, T.; Oda, H.; Sugii, Nobuyuki; Hiramoto, Toshiro

doi:10.1109/snw.2012.6243344

Cited by 18 publications

(16 citation statements)

References 2 publications

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“…Variation of on-state current I on is important and must be decreased since this directly affects the delay variation of circuits. The I on variation was demonstrated to be less than half of bulk [17] and we confirmed a significant reduction of the I on variability for one-million transistors as shown in Figure 7 [16]. The lowest V th values of SOTB and bulk are the same as shown in Figure 6.…”

Section: Sotb Device Technologysupporting

confidence: 82%

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Sugii

Yamamoto

Makiyama

et al. 2014

JLPEA

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Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive V th control

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Section: Sotb Device Technologysupporting

confidence: 82%

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Sugii

Yamamoto

Makiyama

et al. 2014

JLPEA

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show abstract

“…Figure 10 shows cumulative plots of DRV before and after stress. Owing to the small variability of SOTB FETs, 18,19,[29][30][31][32] the worst DRV is less than 0.15 V. In multiple stress application, the DRV of the worst cell improves from 0.130 to 0.115 V. On the other hand, only a small improvement is obtained by single stress application.…”

Section: Resultsmentioning

confidence: 99%

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

Mizutani¹,

Takeuchi²,

Saraya³

et al. 2018

Jpn. J. Appl. Phys.

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We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) siliconon-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

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“…For reference, some results of I on variation Pelgrom plot from previous publications 30) were also plotted.…”

Section: Variability Analysis Using Pelgrom Plotmentioning

confidence: 99%

Cause analysis of width-dependence of on-current variability in thin gate-all-around silicon nanowire MOSFET

Liu¹,

Mizutani²,

Saraya³

et al. 2022

Jpn. J. Appl. Phys.

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In this study, the width dependence of on-current variability in extremely narrow gate-all-around (GAA) silicon nanowire MOSFET down to 2nm width is analyzed by variability decomposition into components as well as analyzing the Pelgrom plot. It is found that the current variability rapidly increases below 4nm mainly due to quantum-effect-induced threshold voltage variability and silicon-thickness-fluctuation-induced mobility fluctuation (μfluctuation). The current variability becomes even worse in 2nm, which is fundamentally caused by line width roughness.

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Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs

Cited by 18 publications

References 2 publications

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

Cause analysis of width-dependence of on-current variability in thin gate-all-around silicon nanowire MOSFET

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