Reduced latency IEEE floating-point standard adder architectures

Beaumont-Smith, A.; Burgess, Neil; Lefrere, S.; Lim, Cheng‐Chew

doi:10.1109/arith.1999.762826

Cited by 44 publications

(28 citation statements)

References 18 publications

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“…IEEE Standard 754 has defined different floating point number representation formats, exceptions and error conditions to support diverse precision requirements [2]. Several researchers [3]- [5] have implemented various architectures for Floating-Point Adders (FPA). The approach outlined in [3] allows for the construction of floating-point units with parameter selection like throughput, latency, and area.…”

Section: Previous Architecturesmentioning

confidence: 99%

An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

Arumalla¹,

Makkena²

2017

IJIES

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Abstract:Reconfigurable architectures have provided a low cost, fast turnaround platform for the development and deployment of designs in communication and signal processing applications. The floating point operations are used in most of the signal processing applications that require high precision and good accuracy. In this paper, an effective implementation of Fused Floating-point Add-Subtract (FFAS) unit with a modification in dual path design is presented. To enhance the performance of FFAS unit for reconfigurable architectures, a dual path unit with a modification in close path design is proposed. The proposed design is targeted on a Xilinx Virtex-6 device and implemented on ML605 Evaluation board for single, double and double extended precision. When compared to discrete floating point adder design, the FFAS unit reduces area requirement and power dissipation as the later shares common logic. A Dual Path FFAS (DPFFAS) unit has reduced latency when compared with FFAS unit. The latency is further reduced with the proposed modified DPFFAS when compared with DPFFAS for reconfigurable architectures.

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Section: Previous Architecturesmentioning

confidence: 99%

An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

Arumalla¹,

Makkena²

2017

IJIES

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“…As well known, proper pipelining increases the throughput of the floating-point adders [13], [14], [20]. Those floating-point adders are split into two or three pipeline stages so that the results are produced every cycle.…”

Section: Chapter 5: a Pipelined Fused Floating-point Add-subtract Unitmentioning

confidence: 99%

Improved Architectures for a Fused Floating-Point Add-Subtract Unit

Sohn

Swartzlander

2012

IEEE Trans. Circuits Syst. I

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“…Ercegovac and Lang [6] contains an overview of the different techniques used to optimize floating-point addition. Most of the earlier work on the FPA design has focused on improving FPA latency [17,[19][20][21]. Oberman [21] proposes the use of two align shifters to improve the latency of their single-precision FPA with only one rounding mode.…”

Section: B Synchronous Floating-point Addersmentioning

confidence: 99%

An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder

Sheikh

Manohar

2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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Abstract-We present the design and implementation of an asynchronous high-performance IEEE 754 compliant doubleprecision floating-point adder (FPA). We provide a detailed breakdown of the power consumption of the FPA datapath, and use it to motivate a number of different data-dependent optimizations for energy-efficiency. Our baseline asynchronous FPA has a throughput of 2.15 GHz while consuming 69.3 pJ per operation in a 65nm bulk process. For the same set of nonzero operands, our optimizations improve the FPA's energy-efficiency to 30.2 pJ per operation while preserving average throughput, a 56.7% reduction in energy relative to the baseline design. To our knowledge, this is the first detailed design of a high-performance asynchronous double-precision floating-point adder.

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Reduced latency IEEE floating-point standard adder architectures

Abstract: The design and implementation of a double precision

Cited by 44 publications

References 18 publications

An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

Improved Architectures for a Fused Floating-Point Add-Subtract Unit

An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder

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