Reducing ALU and Register File Energy by Dynamic Zero Detection

Kim, Soontae

doi:10.1109/pccc.2007.358915

Cited by 9 publications

(7 citation statements)

References 27 publications

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“…The motivation behind ECHP is that the offsets added to the base addresses are small in most cases [3], [4], [5], [6]. The upper bits of the base addresses are very likely to be the same as those of calculated effective addresses.…”

Section: Early Cache Hit Predictormentioning

confidence: 99%

Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction

Lee

Kim

2015

IEEE Trans. Comput.

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On-chip cache memories play an important role in resource-constrained embedded systems by filtering out most off-chip memory accesses. Because cache latency and energy consumption are generally proportional to cache sizes, a small cache at the top level of the memory hierarchy is desirable. Previous work has presented a novel cache architecture called a filter cache to reduce hit time and energy consumption of the L1 instruction cache. However, consideration to the data cache requires a different approach and has not been researched much. In this paper, we propose a filter data cache architecture to effectively adopt the filter cache to the data cache hierarchy. We observed that cache misses occur considerably and they are likely to be continuous when the filter cache is used for the data cache. Those misses cost performance and energy consumption by increasing cache latency and uploading unnecessary data. The proposed filter data cache architecture reduces miss costs using three schemes: early cache hit predictor (ECHP), locality-based allocation (LA), and No Tag Matching Write (NTW). Experimental results show that the proposed filter data cache reduces energy consumption of the data caches by 21% compared with the filter cache, and the energy consumption of the ALU by 27.2 percentage on average. The overheads in terms of area and leakage power are small and the proposed filter data cache architecture does not hurt performance.Index Terms-Filter data cache, early cache hit predictor, locality-based allocation, No Tag-matching Write Ç The authors are with the

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Section: Early Cache Hit Predictormentioning

confidence: 99%

Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction

Lee

Kim

2015

IEEE Trans. Comput.

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“…Our mechanism is based on the key observation that a large number of ALU operands are narrow-width values of which upper bits are all zeros or ones [4], [5], [6], [7], [12]. In modern processors, the ALU is used to execute arithmetic and logical instructions.…”

Section: Predictable Instructionsmentioning

confidence: 99%

“…Our goal is to design a cost-efficient fault-tolerant ALU, which achieves both the performance benefit of hardware redundancy and the cost-efficiency of time redundancy. Key observation is that a wide range of applications use popularly narrow-width values whose upper bits are all zeros or ones [4], [5], [6], [7], [8], [9], [10], [11]. When an ALU performs operations with at least one narrow-width operand (value), the upper bits of their results can be obtained without computations.…”

Section: Introductionmentioning

confidence: 99%

A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU

Hong

Kim

2015

IEEE Trans. Comput.

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Digital circuits are expected to increasingly suffer from more hard faults due to technology scaling. Especially, a single hard fault in ALU (Arithmetic Logic Unit) might lead to a total failure in processors or significantly reduce their performance. To address these increasingly important problems, we propose a novel cost-efficient fault-tolerant mechanism for the ALU, called LIZARD. LIZARD employs two half-word ALUs, instead of a single full-word ALU, to perform computations with concurrent fault detection. When a fault is detected, the two ALUs are partitioned into four quarter-word ALUs. After diagnosing and isolating a faulty quarter-word ALU, LIZARD continues its operation using the remaining ones, which can detect and isolate another fault. Even though LIZARD uses narrow ALUs for computations, it adds negligible performance overhead through exploiting predictability of the results in the arithmetic computations. We also present the architectural modifications when employing LIZARD for scalar as well as superscalar processors. Through comparative evaluation, we demonstrate that LIZARD outperforms other competitive fault-tolerant mechanisms in terms of area, energy consumption, performance and reliability.

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“…The techniques for reducing the required register ports include restricting the number of issued instructions with two source operands [18], writing back destination register with selectivity [19,20], and avoiding unnecessary register access by dynamic zero detection [21]. Another approach is to divide the functional units among two clusters and provide copy of all registers in each cluster, which is used in the Alpha 21264 [22] and 21464 [4] designs.…”

Section: Related Workmentioning

confidence: 99%

A low-power register file based on access queues for multi-issue processors

Xiao

Shen

2014

2014 IEEE/ACIS 13th International Conference on Computer and Information Science (ICIS)

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Multi-port register file is a critical component of high-performance multi-issue processors to exploit instruction parallelisms. However, multiple ports cause such problems as high power and large area. In this paper, we present a novel multi-bank register file (MBRF) architecture to reduce register ports as well as its power and area, which is based on register access queues. The proposed architecture organizes a read queue and a write queue for each register bank, and buffers all the register operations from instructions into the access queues, thus avoiding bank conflicts. At the same time, we use both combine and forward assignment strategies to reduce read and write requests for register file. Experimental results show our techniques are more advantageous in both performance and power saving than the traditional MBRF, achieving 52% and 47% power saving for integer and floating-point programs respectively, with only 1.6% and 2.8% IPC loss.

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Reducing ALU and Register File Energy by Dynamic Zero Detection

Cited by 9 publications

References 27 publications

Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction

Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction

A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU

A low-power register file based on access queues for multi-issue processors

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