Reducing bus delay in submicron technology using coding

Abstract

-In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption.Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2.

Optimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique

“…The average power reduction increase as the input switching activity increases. Transition Pattern Coding Scheme (TPC) proposed by Sotiriadis and Chandrakasan [19] is used to reduction of coupling power in the data bus with encoding. This scheme creates transition matrix for selecting code word patterns such that neighboring bus line changes values in the same direction.…”

Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects

“…In nanoscale technologies, the propagation delay of on-chip interconnect is greatly affected by crosstalk coupling [5] [11]. Depending on the switching behavior of a wire and its neighbors, the delay of a wire in the middle of a bus changes from 0 occurs when there is a transition 010101 (101010) on three adjacent wires [11].…”

A crosstalk aware interconnect with variable cycle transmission

“…'↑', '↓', and '-' are used to represent transitions from 0 to 1, from 1 to 0, and no transition, respectively. The relation between C total and transition patterns of these three wires are analyzed in [10] and are shown in Table 1 1 . Based on the total capacitance, we can get the delay of the target wire using the above formula.…”

“…Since transition patterns in Group 5 and Group 6 are the most problematic ones, they are the focus of our approach. Based on the delay analysis of each wire, the delay 1 The capacitance for the boundary wires can be found in [10]. of an interconnect with 32 wires is computed as the maximum delay among these 32 wires.…”

“…Furthermore, these methods determine the delay associated with data transmission based on the worst-case data transition pattern possible. However, the impact of crosstalk on the delay is data-dependent [10] and different combinations of transition directions of a specific wire and its adjacent wires induce different delays.…”