Reducing losses in three-phase PWM pulsed DC-link voltage-type inverters

Cavalcanti, M.C.; Alves, R.N.; Silva, E.R.C. da; Lima, A.M.N.; Jacobina, C.B.

doi:10.1109/ias.2000.882149

Cited by 3 publications

(1 citation statement)

References 17 publications

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“…In addition, to guarantee the minimization of switching losses for any load power angle the approach in [14] has been extended to QSWDCL inverters, imposing the clamping segments in the vicinity of both the positive and negative current peak for a given load power angle. When the clamping segments cannot be in the vicinity of the current peak, the best choice is to clamp the phase related to the second higher absolute value of current [15].…”

Section: Pwm Techniquementioning

confidence: 99%

An improved quasi-square-wave DC-link converter

Cavalcanti

Silva

Jacobina

Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)

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This paper proposes a Quasi-Square-Wave DC Link (QSWDCL) converter, which improves the performance of an existing topology. The proposed circuit provides zero-DC-link voltage notches, during which the inverter switching is effected, and imposes a minimum DC bus voltage stress to the PWM inverter. Simple design conditions are offered. Simulated and experimental results demonstrate the validity of the proposed topologies.

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Section: Pwm Techniquementioning

confidence: 99%