Reducing power dissipation of register alias tables in high-performance processors

Küçük, Gürhan; Ergin, Oğuz; Ponomarev, Dmitry; Ghose, Kanad

doi:10.1049/ip-cdt:20050009

Cited by 7 publications

(9 citation statements)

References 11 publications

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“…Along the same line, Kucuk et al [15] further reduce the number of accesses to the front-end RAM by forwarding results of previous accesses performed by nearby instructions.…”

Section: B Hardware Complexitymentioning

confidence: 99%

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery

Petit

Ubal

Sahuquillo

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-Modern superscalar processors implement register renaming by using either RAM or CAM tables. The design of these structures should address their access time and misprediction recovery penalty. While direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. Although they are more complex and slower, CAMs usually match the processor cycle in current designs. However, they do not scale with the number of physical registers and the pipeline width.In this paper we present a new hybrid RAM-CAM register renaming scheme, which combines the best of both approaches. In a steady state, a RAM provides the current mappings quickly; on mispeculation, a low-complexity CAM enables immediate recovery and further register renaming. Compared to an ideal CAM in a 4-way state-of-the-art superscalar microprocessor, and for almost the same performance (1% slowdown) and area (95% of the ideal CAM size), the proposed scheme consumes about 90% less dynamic energy. I. INTRODUCTIONHigh performance microprocessors implement out-oforder and speculative execution to increase performance. In this context, many mechanisms have been devised aimed at enhancing the amount of instructions executing concurrently. These microarchitectural mechanisms require register renaming techniques in order to overcome write after read (WaR) and write after write (WaW) data hazards.Register renaming techniques distinguish two kinds of registers: logical and physical registers. Logical or architected registers refer to those used by the compiler, while physical registers are those actually implemented in the machine. Typically, the number of physical registers is quite larger than the number of logical registers. When an instruction that produces a result is decoded, the renaming logic allocates a free physical register. Then, the destination logical register is said to be mapped to that physical register. After that, subsequent data dependent instructions rename their source logical registers to access this physical register. In addition, to deal with program execution correctness, the register renaming circuitry must also recover the register mapping table on mispeculation and release the physical registers allocated to mispeculated instructions. To this end, some microprocessors perform checkpoints of the renaming

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“…Along the same line, Kucuk et al [15] further reduce the number of accesses to the front-end RAM by forwarding results of previous accesses performed by nearby instructions.…”

Section: B Hardware Complexitymentioning

confidence: 99%

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery

Petit

Ubal

Sahuquillo

et al. 2009

2009 IEEE International Conference on Computer Design

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“…With the same aim, Kucuk et al [16] further reduce the number of accesses to the front-end RAM by forwarding results of previous accesses performed by instructions nearby.…”

Section: Related Workmentioning

confidence: 99%

Efficient Register Renaming and Recovery for High-Performance Processors

Petit

Ubal

Sahuquillo

et al. 2014

IEEE Trans. VLSI Syst.

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Petit Martí, SV.; Ubal Tena, R.; Sahuquillo Borrás, J.; López Rodríguez, PJ. (2014). Efficient register renaming and recovery for high-performance processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22 (7) Modern superscalar processors implement register renaming by using either RAM or CAM tables. The design of these structures should address both access time and misprediction recovery penalty. While direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. However, the presence of associative ports in CAMs prevents them from scaling with the number of physical registers and pipeline width, negatively impacting performance, area, and energy consumption at the rename stage. In this paper, we present a new hybrid RAM-CAM register renaming scheme, which combines the best of both approaches. In a steady state, a RAM provides fast and energy-efficient access to register mappings. On misspeculation, a low complexity CAM enables immediate recovery. Experimental results show that in a 4-way state-of-the-art superscalar processor, the new approach provides almost the same performance as an ideal CAM-based renaming scheme, while dissipating only between 17% and 26% of the original energy and, in some cases, consuming less energy than purely RAM-based renaming schemes. Overall, the silicon area required to implement the hybrid RAM-CAM scheme does not exceed the area required by conventional renaming mechanisms.

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“…The second category includes work on reducing the number of RAT GCs or RAT ports while maintaining performance (e.g., [14], [20]). This paper complements these studies by focusing on both IPC and latency.…”

Section: G Checkpointed Rat: Related Workmentioning

confidence: 99%

“…Equation (13), --, calculates the number of NOR gates driven by each NAND gate. Given by (14), the length of the wire between two NOR gates fed by a specific NAND gate of the predecode stage is a function of the RAT cell's height and NoGC. The corresponding resistance and capacitance are calculated by (15).…”

Section: ) Component Delay-decodermentioning

confidence: 99%

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On the Latency and Energy of Checkpointed Superscalar Register Alias Tables

Safi

Moshovos

Veneris

2010

IEEE Trans. VLSI Syst.

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Abstract-This paper investigates how the latency and energy of register alias tables (RATs) vary as a function of the number of global checkpoints (GCs), processor issue width, and window size. It improves upon previous RAT checkpointing work that ignored the actual latency and energy tradeoffs and focused solely on evaluating performance in terms of instructions per cycle (IPC). This work utilizes measurements from the full-custom checkpointed RAT implementations developed in a commercial 130-nm fabrication technology. Using physical-and architectural-level evaluations together, this paper demonstrates the tradeoffs among the aggressiveness of the RAT checkpointing, performance, and energy. This paper also shows that, as expected, focusing on IPC alone incorrectly predicts performance. The results of this study justify checkpointing techniques that use very few GCs (e.g., four). Additionally, based on full-custom implementations for the checkpointed RATs, this paper presents analytical latency and energy models. These models can be useful in the early stages of architectural exploration where actual physical implementations are unavailable or are hard to develop. For a variety of RAT organizations, our model estimations are within 6.4% and 11.6% of circuit simulation results for latency and energy, respectively. This range of accuracy is acceptable for architectural-level studies.Index Terms-Computer architecture, delay and power modeling, implementation, microprocessors, register alias table (RAT).

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Reducing power dissipation of register alias tables in high-performance processors

Cited by 7 publications

References 11 publications

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery

Efficient Register Renaming and Recovery for High-Performance Processors

On the Latency and Energy of Checkpointed Superscalar Register Alias Tables

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