Reducing pressure in bounded DBT code caches

Abstract

Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight constraints on memory and performance. A DBT uses a software-managed code cache to hold blocks of translated code. To minimize overhead, the code cache is usually large so blocks are translated once and never discarded. However, an embedded system may lack the resources for a large code cache. This constraint leads to significant slowdowns due to the retranslation of blocks prematurely discarded from a small code cache. This paper addresses the problem and shows how to impose a tight size bound on the code cache without performance loss. We show that about 70% of the code cache is consumed by instructions that the DBT introduces for its own purposes. Based on this observation, we propose novel techniques that reduce the amount of space required by DBT-injected code, leaving more room for actual application code and improving the miss ratio. We experimentally demonstrate that a bounded code cache can have performance on-par with an unbounded one.

Addressing the challenges of DBT for the ARM architecture

“…Strata is configured to form dynamic basic blocks [18], which minimizes code growth (important for embedded systems) [2]. An effectively unbounded code cache is used.…”

“…If a fragment does not exist for the application address, the instructions at the address are translated. A 2 The pc register always contains the address of the current instruction + 8.…”

“…For this reason, DBT has attracted attention for embedded systems [2,3,5,6,9,17,22]. Several compelling uses of DBT in embedded systems have been explored.…”

DBT path selection for holistic memory efficiency and performance

“…Most DBTs support general-purpose computing platforms. Pin [25], DELI [9] and Strata [1,2,26] are DBTs that support embedded platforms.…”

“…We also found that factoring in data structure sizes impacts the relative memory demand of path selection strategies. Previous approaches placed the memory limit on the code cache only [1,2,12,16], leading to inaccurate interpretation of performance results. Additionally, previous work has researched both code selection [10,18,19] and linking strategies [3,6,9,22,25] but from the performance perspective only.…”