Reducing SoC simulation and development time

Rowen, Chris

doi:10.1109/mc.2002.1106176

Cited by 23 publications

(9 citation statements)

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“…The students' knowledge on HDL languages, such as VHDL and Verilog HDL, is an essential requirement to learn processor design [10]. However, insufficient training in HDL for undergraduate students was reported in many U.S.…”

Section: Previous Workmentioning

confidence: 99%

A Processor Design Course Project: Creating Soft-Core MIPS Processor Using Step-by-Step Components’ Integration Approach

Elkateeb¹

2011

IJIET

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Abstract-Design and implementation of a soft-core MIPS processor using field-programmable gate array (FPGA) technology will be addressed in this paper. Teaching processor architecture and design is considered the key element of the student learning in the undergraduate Computer Engineering program; as such, this project was developed to enrich students' experience in this field. This paper presents a practical introduction to soft-core processor design through the use of step-by-step integrating of the processor's components. Students implemented their processors using Xilinx ISE design tools and downloaded their designs to Xilinx ML 501 FPGA boards, which used Xilinx Virtex 5 chips. A designed and developed soft-core processor provided students with a starting point for applying their designed processors in follow-up courses such as Embedded Systems and Senior Design Project. Students' assessment of the soft-core processor design was analyzed, which indicated that they are confident in confronting the next step of constructing advanced processor architecture.Index Terms-MIPS processor, field-programmable gate array (FPGA), Xilinx design tools, VHDL.

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Section: Previous Workmentioning

confidence: 99%

A Processor Design Course Project: Creating Soft-Core MIPS Processor Using Step-by-Step Components’ Integration Approach

Elkateeb¹

2011

IJIET

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“…Design teams may often spend as much as 90% of their development effort on block or system level verification [13]. Enhancement in design productivity can achieved using design for reuse strategies throughout the entire span of the project development from initial design through to functional test and final verification [14,10,4].…”

Section: Design For Reusementioning

confidence: 99%

QR Recursive Least Squares IP Core Example

Lightbody

Woods²

2008

15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems (Ecbs 2008)

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With transistor counts increasing at a rate of 58% per year and design productivity only growing at 21% per year, there is an important need to develop new design approaches to close this gap. This paper outlines the process by which IP cores are generated and shows how the design methodology can be improved to enhance their usability. The process is demonstrated using a recursive least squares (RLS) adaptive filter example.

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“…Once all the electronic modules were produced, generating the whole system would just be a matter of attaching all of them to the on-chip bus. This is a natural process to design a system on a chip [32].…”

Section: A On-chip Busmentioning

confidence: 99%

Design of a Master Device for the Multifunction Vehicle Bus

Jiménez

Martin

Bidarte

et al. 2007

IEEE Trans. Veh. Technol.

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This paper presents the design of a network master device for the multifunction vehicle bus. An analysis of the specifications for this bus administrator reveals that the functional design can be arranged in 14 operational blocks and in a special memory for communication data known as the Traffic Store. System-on-a-chip strategies have been adopted in order to cope with this great complexity. The architecture includes a standard on-chip bus, which is aimed at interconnecting all the modules as cores attached to it by an established interface. In this way, creation flow can be concurrent, and design for reuse is made easier. The entire architecture has been coded in SystemC not only for verification purposes but also for setting the intermediate point in the refinement process toward the register transfer-level design. After validating this executable description by simulation, the hardware/software partition has been performed following the codesign philosophy. Estimations about consumed silicon area, hardware response time, occupied program memory, and software execution time have been made in order to calculate a cost function for each functional block: the cost-performance difference. From these, an optimum hardware/software architecture has been obtained. As a result, the electronic platform for the master device has been generated on a field-programmable gate array. The final implementation contains a soft processor as the main component, a ROM, a RAM, some internal registers, and the Traffic Store.Index Terms-Design methodology, logic design, rail transportation electronics, train communication network (TCN).

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Reducing SoC simulation and development time

Cited by 23 publications

References 0 publications

A Processor Design Course Project: Creating Soft-Core MIPS Processor Using Step-by-Step Components’ Integration Approach

A Processor Design Course Project: Creating Soft-Core MIPS Processor Using Step-by-Step Components’ Integration Approach

QR Recursive Least Squares IP Core Example

Design of a Master Device for the Multifunction Vehicle Bus

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