Reducing the impact of internal upsets inside the correlation process in GPS Receivers

Abstract

This paper 1 examines two approaches to deal with internal logic upsets inside correlation process used in the tracking process of GPS receivers. These upsets can be produced due to process/voltage and temperature variations coupled with increased advancement of CMOS technology. If any upset occurs when computing the correlation function during each 10 ms, then errors are propagated in tracking loops, resulting in a loss of the GPS signal tracking and a distorted position given by the receiver. Results of experiments using a GPS receiver design are presented in this paper to evaluate the performance of each method. The two proposed solutions (the Feedback freezing loop (FFL) and the Last Correct Value (LCV) methods) offer a big interest compared to the classical Triple Modular Redundancy (TMR) method since they provide the same performance as the TMR with low area complexity. This work can be extended to any system using feedback loops information.

Hardware error correction using local syndromes

“…The extension is straightforward: to the N functions 2 In [10], in case of error, the previous last correct value is given to a feedback filter in order to limit the propagation of error for example …”

Demo: Localisation in a faulty digital GPS receiver

“…Position given by a noiseless GPS receiver X(t) (color orange), by a faulty GPS receiver without adding the fault tolerant technique (color red), by a faulty GPS receiver when using the fault tolerant technique (color blue), displayed using Google earth in order to have a complete GPS receiver (Radio Frequency and digital processes). Although, fault tolerant techniques that have been proposed in [5], [6] and [7] to protect, respectively, the Gold code generator, the the Numerically Controlled Oscillator and the correlation will be implemented in the noisy receiver to evaluate the robustness of the complete GPS receiver against transient errors. An ASIC will replace the FPGA target once the study of the trade-off between the complexity and the performance of the GPS receiver is achieved.…”

Improving the Performance of the Carrier Tracking Loop for GPS Receivers in Presence of Transient Errors due to PVT Variations

“…In [10] and [11], strategies have been proposed and evaluated for upset protection in the Gold sequence generators and the Numerically Controlled Oscillator (NCO) respectively. The authors of [12] presents two approaches to deal with internal logic upsets inside correlation process used in the tracking process of GPS receivers.…”