This paper 1 examines five strategies for upset protection in Gold sequence generators used to maintain signal acquisition in GPS receivers. This work is motivated by the increased prevalence of single-event upsets in ultra low-power GPS receivers. If any upset occurs in the Linear Feedback Shift Register (LFSR) modules, then the corresponding satellite signal must be re-acquired, resulting in high energy expenditure and time delay. We evaluate the performance and complexity of methods based on error correction and modular redundancy.

This paper 1 examines two approaches to deal with internal logic upsets inside correlation process used in the tracking process of GPS receivers. These upsets can be produced due to process/voltage and temperature variations coupled with increased advancement of CMOS technology. If any upset occurs when computing the correlation function during each 10 ms, then errors are propagated in tracking loops, resulting in a loss of the GPS signal tracking and a distorted position given by the receiver. Results of experiments using a GPS receiver design are presented in this paper to evaluate the performance of each method. The two proposed solutions (the Feedback freezing loop (FFL) and the Last Correct Value (LCV) methods) offer a big interest compared to the classical Triple Modular Redundancy (TMR) method since they provide the same performance as the TMR with low area complexity. This work can be extended to any system using feedback loops information.

Four strategies for upset protection in NCO (Numerically controlled oscillator) generators are presented and compared in this paper 1. This work is motivated by the increased prevalence of single event upsets due to process/voltage/temperature variations coupled with the increased advancement of CMOS technology. The occurrence of these upsets in the GPS context (the system under the test in this paper) can lead to a loss of the GPS signal tracking, then the corresponding satellite signal must be re-acquired resulting in high energy expenditure and time delay. It can result also in a corrupted position given by the GPS receiver. Results of experiment using a GPS receiver design are presented in this paper to evaluate the performance of proposed methods. This work can be extended and generated to any system using feedback loops information.

The increase in integration density and the requirement of low power supplies to reduce energy consumption can make circuits more and more sensitive to upsets errors. The loss of robustness increases with process/voltage and temperature (PVT) variations. This paper 1 shows that the impact of errors that appear when computing the estimation of the Doppler offsets in a GPS application can be greatly reduced by tuning appropriately the carrier filter bandwidth. The effectiveness of the proposed was proven by comparing the performance a faulty GPS receiver to a non-faulty (noisy-free) GPS receiver at two levels: the standard deviation of the tracking error variance (by theory and by simulation) as well as the standard deviation between positions given by the faulty (noisy) and non-faulty (the noiseless) GPS receivers. Modifying properly the optimal filter bandwidth values gives astonishing results in terms of robustness against errors. The modification of the bandwidth filter values introduces almost no position degradation in a noise-free GPS receiver (only 11 cm in average). With 40 % of error, the standard deviation of the error in the position does not exceed 2 m by increasing the PLL bandwidth while the tracking loop does not support more than 6% of errors.

Abstract-Increasing the integration density offers the possibility for designers to built very complex system on a single chip. However, approaching the limits of integration, circuit reliability has emerged as a critical concern. The loss of reliability increases with process/voltage and temperature (PVT) variations. Faults can appear in circuits which can affect the system behaviour and lead to a system failure. Therefore it is increasingly important to build more fault tolerant resilient system. This paper 1 proposes a new fault tolerant scheme, the Duplication with Syndrome based Correction (DSC) scheme. Two criteria were considered to evaluate the proposed scheme: the reliability (probability that no error appears in the output of the architecture) and the hardware efficiency of the architecture. Results show that the DSC scheme reduces the complexity by 32%, compared to the classical Triple Modular Redundancy (TMR) scheme, while maintaining a level of reliability closed to the TMR. The paper shows also an example of signal processing applications where the DSC has been used to protect the correlation function and filters inside the tracking loops of the Global Positioning System (GPS) receiver.